Abstract: An integrated circuit and method of manufacturing therefor. In one embodiment, the integrated circuit includes a substrate with an insulator and a capacitor formed over the substrate. The integrated circuit further includes an adhesive formed over the insulator. The integrated circuit still further includes a micromagnetic device. The micromagnetic device includes a ferromagnetic core formed over the adhesive. The adhesive forms a bond between the insulator and the ferromagnetic core to secure the ferromagnetic core to the substrate. The micromagnetic device also includes at least one winding, located proximate the ferromagnetic core, to impart a desired magnetic property to the ferromagnetic core. The micromagnetic device is electrically coupled to the capacitor.
Type:
Grant
Filed:
June 22, 1999
Date of Patent:
July 3, 2001
Assignee:
Agere Systems Guardian Corporation
Inventors:
Dean P. Kossives, Ashraf W. Lotfi, Lynn F. Schneemeyer, Michael L. Steigerwald, R. Bruce Van Dover
Abstract: An electrical contact, preferably made from a gold-plated, beryllium-copper flat stock which allows radio-frequency signal to pass with low noise, is provided within a housing. The electrical contact has two arms for contact with two external circuits. The electrical contact further has a pivot for allowing the electrical contact to adjust within the housing. The housing supports the electrical contact and is provided with a pivot point, such as a non-conducting rubber tip, for meeting the pivot of the electrical contact. The housing combined with one or more of the electrical contacts results in a testing port especially suited for providing high frequency communication between an electrical testing fixture and a device under test, such as a high-frequency hybrid integrated circuit.
Type:
Grant
Filed:
January 10, 2000
Date of Patent:
June 26, 2001
Assignee:
Agere Systems Guardian Corporation
Inventors:
Stephen Michael Thompson, Gerard J. Mietelski, William E. Fulmer
Abstract: A process for the manufacture of semiconductor integrated circuits is described in which the defect density due to conductive particle debris formed at the edge of the wafer is reduced by burying the edges of the metal layers in a tapered step configuration, so that the maximum steps in the interlevel and final dielectric layers are essentially the same as the thickness of the metal layers.