Abstract: One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.

Abstract: A circuit for audibly indicating at least one state of a television receiver includes memory operative to store at least one audio file, and a controller. The controller is operative during a power-on interval of the television receiver to forward the at least one audio file to an audio indicating device associated with the television receiver for audibly indicating the at least one state of the television receiver.

Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

Abstract: In one embodiment, an algorithm dynamically selects a method for reducing distortion in a multi-carrier modulated signal, such as an orthogonal frequency division multiplexing (OFDM) signal. The algorithm directs a transmitter to transmit peak-to-average power ratio (PAPR)-reduction signals over reserved tones (i.e., frequencies) if reserved tones are available. If reserved tones are not available, then the algorithm directs the transmitter to transmit PAPR-reduction symbols over free tones if free tones are available. If the free tones for this transmitter are used by adjacent transmitters, then interference-reduction techniques may be used to reduce interference with the adjacent transmitters. If reserved tones and free tones are not available, then the transmitter may use an alternative method to reduce distortion, such as successive clipping and filtering. In another embodiment, the transmitter may transmit PAPR-reduction symbols over both free and reserved tones, if available.

Abstract: A method of using an intercom on a cordless telephone during an active call. The active call is put on hold while the intercom is in use. Once the call is re-activated, the intercom is shut off. This system may be designed for a cordless telephone with one handset or a plurality of handsets.

Abstract: A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: In one embodiment, a wireless device for a wireless data communication system including the wireless device and a base station. The base station includes a plurality of first groups and a signal-processing unit. Each first group includes a receiver and at least one antenna connected to the receiver. The signal-processing unit includes memory and a processor adapted to process signals received by the first groups using a Maximum Likelihood Detection (MLD) method. The wireless device includes a plurality of second groups, each second group adapted to transmit a wireless signal to at least one first group via a corresponding communication channel. Each second group further includes a transmitter and at least one antenna connected to the transmitter.

Abstract: In one embodiment, a virtual gateway mediates between a dual-mode subscriber device and an IP-based PBX. In particular, the virtual gateway includes a WLAN interface for communicating with the dual-mode subscriber device and a network interface (wired or wireless) for communicating with the IP-based PBX over the Internet. As such, the virtual gateway may relay voice and call control instructions between the dual-mode subscriber device and the IP-based PBX, and may provide the same call control functions to the dual-mode subscriber device provided by the call control processor in existing dual-mode phones. The embodiment further provides a dual-mode subscriber device suitable for operation with the virtual gateway. Because the dual-mode subscriber device does not require a call control processor, the battery life and cost of the device are significantly improved.

Abstract: Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.

Abstract: In one embodiment, the present invention is a method for detecting an echo path change (EPC) in a telecommunications network. The method detects whether the effectiveness of echo cancellation of an echo canceller has decreased relatively significantly. Once a relatively significant decrease is detected, the method determines whether the decrease was an EPC or an inadvertent detection of double talk (DT). In particular, the method considers whether echo is effectively cancelled over a hangover period. Further, echo return loss (ERL) estimates are generated over the hangover period and compared to a lowest-possible ERL for the network. If both (1) echo cancellation is ineffective and (2) a sufficient number of ERL estimates are not below the worst-case ERL, then an EPC decision is made. If either (1) echo cancellation is effective or (2) a sufficient number of ERL estimates are below the worst-case ERL, then a DT decision is made.

Abstract: In one embodiment, a transmitter converts digital input data into combined-OFDM signals and a receiver recovers data from the transmitted combined-OFDM signals. For transmission, digital data is mapped into data symbols using a commonly known modulation technique, such as QAM or DQPSK. The data symbols are subsequently divided into two or more groups according to a specified grouping pattern. Each group of data symbols is then converted into a separate OFDM subsymbol using IFFT processing. The OFDM subsymbols are then combined according to a specified combining pattern to create a combined-OFDM symbol. Combined-OFDM symbols are then prepared for transmission by affixing cyclic prefixes, converting the symbols to analog format, and performing spectral shaping of the analog signal. Upsampling may be employed to increase the signal bandwidth. In alternative embodiments, OFDM subsymbols may be combined using interleaving to create an interleaved-OFDM symbol.

Abstract: Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Abstract: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

Abstract: A method and apparatus are disclosed for detecting an address mark in a data stream having a preamble followed by the address mark. The end of the preamble is detected in the data stream, which is then used to open a window to search for the address mark. If the address mark is not detected during the window, the search for the address mark is restarted. The window can have a duration based on a length of the address mark. The address mark can be, for example, a servo address mark following a servo preamble or a read address mark following a read preamble. The preamble can have a 2T pattern and the preamble can be detected by determining if energy associated with a 2T frequency is greater than energy associated with a non-2T frequency. The end of the preamble can be performed by an EndOf2T detector that detects a break in an expected bit pattern.

Abstract: A packet network employs frame aggregation to reduce the number of physical-layer frames employed to transfer a given amount of user data. A packet network might employ physical (PHY) and medium access control (MAC) layers of a wireless local area network (WLAN) operating in accordance with one or more IEEE 802.11 standards. Frame aggregation combines several separate, higher-layer frames with user data into one PHY-layer frame, thus increasing the amount of user data per PHY-layer frame transmitted. Frame aggregation improves the efficiency by reducing both PHY-layer overhead and MAC-layer overhead.

Abstract: In one embodiment, a receiver for providing a virtual local channel in a broadcast radio system that transmits a plurality of sets of local content corresponding to a plurality of different geographic regions is disclosed. The receiver includes a detector (e.g., 432), adapted to determine a regional identifier for the receiver. The receiver also includes a channel selector (e.g., 412), adapted to obtain a selected set of local content from among the plurality of sets of local content, based on the determined regional identifier, for inclusion in the virtual local channel. The determined regional identifier identifies the geographic region associated with the selected set of local content.

Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Abstract: In one embodiment, the presence of double talk (DT) is detected in a telecommunications network having a near-end user and a far-end user. The energies of both (1) a signal received from the far-end user by the near-end user and (2) a signal to be communicated from the near-end user to the far-end user are computed. An echo return loss (ERL) estimate is calculated based on the energy calculations, and a preliminary decision is made as to whether DT is present based on the ERL estimate and the energy calculations. If DT is detected, then a counter is set to a hangover value. If DT is not detected, then the counter is reduced. This process is repeated, and, for each iteration, a final decision as to whether DT is present is made based on the counter value.