Abstract: A ground- or roof-top-based repeater in an OFDM system uses multiple transmission antennas to transmit multiple identical OFDM signals. Dithering is performed by introducing a slight variable-frequency phase offset to all but one of the multiple identical transmitted OFDM signals. The effective overall channel is more dynamic and provides spatial diversity to minimize long periods of fading in fading subchannels of the OFDM signals when the receiver is in a slow moving or stationary situation. To overcome the additional cancellation problem that can occur when two or more of the transmitting antennas are (i) in a line-of-site position with the receiver and (ii) approximately the same distance from the receiver, a delay is deliberately introduced to make the delayed signals appear to be reflected signals. This delay will not negatively impact the OFDM receiver performance as long as the delay is within the guard interval used in the OFDM process.

Abstract: In one embodiment, a method for processing a transport block having a MAC-hs protocol data unit (PDU) and a corresponding checksum in an HSDPA-compatible (high-speed downlink packet access) receiver in a 3GPP wireless communication network, the method including: (a) recovering the transport block, (b) performing, substantially in parallel: (i) a cyclic redundancy check (CRC) on the transport block to determine whether the transport block passes or fails, and (ii) MAC (media access control) disassembly to generate a modified MAC-hs PDU, and (c) determining whether to perform reordering-queue distribution and reordering on the modified MAC-hs PDU based on whether the transport block passes or fails. By performing the CRC check and disassembly substantially in parallel, processing efficiencies may be gained.

Abstract: In one embodiment, a wireless device having two or more antennas. The wireless device substantially concurrently determines (a) using a first antenna, whether a first communications service is available for data transfer, and (b) using a second antenna, whether a second communications service is available for data transfer. After determining that at least one communications service is available for data transfer, the wireless device uses both antennas to transfer data using a selected communications service.

Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Abstract: Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host.

Abstract: An electronic audio device with a digital audio output channel in which an amplifier output voltage is gradually ramped up and down to avoid causing a popping sound when the device is turned on and off. This is accomplished without employing any additional hardware, by incrementally changing a digital input word applied to a digital audio source, such as a DSP, so as to gradually change the amplifier output voltage between a minimum, such as zero volts, and a DC working voltage. On powering up, the amplifier is only turned on after the digital word is applied, but while it still results in a minimum amplifier output, and on powering down the amplifier is turned off after it's output has been ramped down, but before removing the digital input word. Sources and output channels can also be switched over by powering down, and then powering up, following the same method.

Abstract: The disclosure provides a wireless device for use in a wireless network, systems and methods for identifying radar signals and for giving the wireless network a radar-avoidance capability. In one embodiment, the wireless device includes: (1) a pulse analyzer configured to make a determination whether a received pulse is a radar pulse and not a wireless network pulse and (2) a pulse reporter coupled to the pulse analyzer and configured to generate, if the determination is positive, a report thereof for transmission over the wireless network to a central aggregation node thereof.

Abstract: One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: In one embodiment, a method for writing data to a storage-device array (i) including three or more storage devices and (ii) having a plurality of stripes, each stripe having two or more sector levels, each sector level containing one sector on each storage device in the array at corresponding addresses across the storage devices. The method includes: (a) calculating a parity index based on (i) an index value for a current stripe and (ii) the number of storage devices in the array, the parity index identifying a first storage device for parity data for the current stripe; and (b) at each sector level of the current stripe: (b1) writing parity data to the first storage device identified by the parity index; and (b2) writing information to the remaining storage devices.

Abstract: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.