Abstract: A telephone line interface circuit with event detection capabilities is provided that screens out transient signals and provides an indication to the line side that an actual event has occurred; so that appropriate discrimination circuitry is powered up to determine the exact nature of the actual event only when needed. An event detector develops an AC signal that represents the events to be detected. This AC signal is timed to determine its sustained rate. The sustained rate has a timing threshold which is higher than a transient that occurs on the line. If the incoming signal does not meet the required threshold timing, it is disregarded as being transient and no action is taken. If the incoming signal meets the threshold requirement, the line interface circuit switches to the full power mode and facilitates the actual data transmission.

Abstract: A system for deriving multiple channels from four-wire residential telephone wiring. The invention provides two voice channels and two, or more, data channels on common residential telephone wiring. The voice channels occupy a normal telephone bandwidth, in the range of approximately zero Hz to 3500 Hz. With this channel placement, ordinary telephonic devices can use the channels, without a requirement of frequency-shifting. Above these voice-channel frequencies, data channels are provided, for internal communication within the residence.

Abstract: A method for making a radio frequency (RF) component includes forming a dielectric layer on a semiconductor substrate and forming and patterning a conductive layer on the dielectric layer to define the RF component. The dielectric layer may include SiN, the conductive layer may include aluminum, and the semiconductor substrate may include silicon, for example. At least one opening may be formed through the RF component at least to the semiconductor substrate. Moreover, the at least one opening may either extend into the semiconductor substrate or substantially terminate at a surface of the semiconductor substrate. The RF component may then be released from the semiconductor substrate by exposing the semiconductor substrate to an etchant passing through the at least one opening to the semiconductor substrate. Releasing the RF component may include exposing the semiconductor substrate to a dry etchant, such as XeF2, for example.

Abstract: A method and apparatus for reducing deep fading of signals in satellite-based communications systems employing terrestrial repeater stations by shifting the phase of the signals transmitted from each terrestrial repeater station by a different amount so that the signals are transmitted from each terrestrial repeater station and received at a receiver at different phases, thereby effectuating time diversity in such signals to reduce deep fading of the signals. The method and apparatus can be used in CDMA and OFDM systems.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising an insulating layer that includes a seed layer formed on a silicon substrate. The seed layer is formed by exposing a hydrogen-terminated surface of the silicon substrate in a substantially oxygen-free environment to a seed layer precursor comprising a methylated metal. Forming the insulating layer further includes depositing a dielectric material on the seed layer.

Abstract: A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

Abstract: The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.

Abstract: An improved process for fabricating emitter structures from nanowires, wherein the nanowires are coated with a magnetic material to allow useful alignment of the wires in the emitter array, and techniques are utilized to provide desirable protrusion of the aligned nanowires in the final structure. In one embodiment, nanowires at least partially coated by a magnetic material are provided, the nanowires having an average length of about 0.1 &mgr;m to about 10,000 &mgr;m. The nanowires are mixed in a liquid medium, and a magnetic field is applied to align the nanowires. The liquid medium is provided with a precursor material capable of consolidation into a solid matrix, e.g., conductive particles or a metal salt, the matrix securing the nanowires in an aligned orientation. A portion of the aligned nanowires are exposed, e.g., by etching a surface portion of the matrix material, to provide desirable nanowire tip protrusion.

Abstract: The present invention provides a method of manufacturing an interdigitated semiconductor device. In one embodiment, the method comprises simultaneously forming first electrodes adjacent each other on a substrate, forming a dielectric layer between the first electrodes, and creating a second electrode between the first electrodes, the second electrode contacting the dielectric layer between the first electrodes to thereby form adjacent interdigitated electrodes. An interdigitated capacitor and a method of manufacturing an integrated circuit having an interdigitated capacitor are also disclosed.

Abstract: A thin film resonator comprising a piezoelectric material and having a controllable or tunable resonant frequency. The resonator is formed on a substrate having a cavity formed therein below the piezoelectric film material. A bending electrode is disposed within the cavity and the application of a voltage between the bending electrode and one of the resonator electrodes, creates an electric field that causes the substrate region to bend. These stresses caused: by the bending are transferred to the thin film resonator, subjecting the piezoelectric film to stresses and thereby changing the resonant properties of the thin film resonator.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising an insulating layer that includes a seed layer formed on a substrate. The seed layer is formed by removing hydrogen from the substrate, depositing a seed layer precursor and exposing the precursor to excited atoms to form a seed layer on the substrate. In addition to serving as a template for the growth of a high K dielectric layer, the seed layer retards the undesirable oxidation of the silicon surface thereby improving the performance of active devices that include the insulating layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Abstract: A method of identifying an integrated circuit device based on the initial state of certain memory cells within a memory array of the integrated circuit device. For many cells in the memory array the initial state is relatively consistent at each power-up, due to mismatches between the transistors that form each memory cell. Thus these consistent initial states provide a signature of the memory array and the integrated circuit device.

Abstract: A priority history module monitors the past history of data packets submitted to the hardware queue with respect to two or more priority levels. The priority queuing module may use any suitable arbitration or other algorithm to order the submission of data packets of varying priorities from the various software data queues, as is otherwise conventional, particularly when data packets of all types of priorities are currently waiting for submission to the transmit data queue. However, when an absence of a particular priority level occurs (e.g., when no highest priority data packets are waiting for submission), then latency of the transmit data queue is adaptively balanced with throughput of the transmit data queue, in accordance with the principles of the present invention. Latency of the data packets currently in the relevant data queue may be estimated to further qualify the adaptively adjusted limit to the data queue.

Abstract: A method is disclosed for producing a high-resolution patterned layer on a substrate for use in making electronic devices. The method comprises micro-printing an inked pattern on a substrate with use of a rotatable stamp; passing the substrate to an apparatus for etching or depositing materials on the substrate, where the inked pattern guides the etching or deposition of material; and then optionally removing the inked pattern from the substrate with the application of heat, ultraviolet light, or wet chemical means. A high-quality transistor with a 2-micron channel length may be fabricated using the inventive method. The method is compatible with rapid, reel-to-reel patterning and useful for a range of applications.

Abstract: A synchronization method and apparatus for detecting and synchronizing asynchronous signal data pulses. The synchronization system passes individual data pulses through two parallel synchronization sub-circuits, alternating synchronization sub-circuits for each succeeding pulse, and combines the output of the parallel synchronization sub-circuits to create a single synchronous signal.

Abstract: For use in a CDMA receiver having a Viterbi decoder, a system for, and method of, performing one-pass blind transport format detection (BTFD) with respect to a received frame and a WCDMA receiver incorporating the system or the method. In one embodiment, the system includes: (1) a traceback circuit that performs a zero state BTFD traceback function with respect to at least a Viterbi-decoded portion of the frame, the traceback function being dependent upon a relative position of a BTFD checkpoint and generating hard decision bits and (2) a BTFD point selection circuit, coupled to the traceback circuit, that employs the hard decision bits to determine a location of a BTFD point with respect to the frame.

Abstract: The present invention provides a method of manufacturing an antenna structure. In one embodiment, the method includes forming an antenna trace on a substrate proximate a ground plane of the substrate. In addition, the method includes creating an insulation region extending through the substrate and located between the antenna trace and the ground plane.

Abstract: A line powered data access arrangement (DAA) is disclosed which adaptively allows proper operation with power supplied from a telephone line as conditions warrant, while at the same time satisfying the relevant requirements of many countries. In the line powered codec, a startup procedure for the international line powered codec uses register settings, e.g., country-specific register settings, which are powered and maintained from the low voltage side (e.g., from the PC or modem side) of the line powered codec. In this way, even during low line power conditions the programmed state of the line powered codec can be maintained, thus a default condition will not necessarily returned to by the line powered codec upon reset due to a power loss in the telephone line. In another aspect, a charge storage device such as a charge capacitor is charged from a charge pump formed from a differential clock signal from the low voltage side.