Abstract: Two or more digital signals are encoded using two or more respective line codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As such, the two or more encoded signals may be combined and transmitted via a single physical medium with little or no interference. A transmitter for encoding and transmitting the digital signals contains line coders for encoding the digital signals and a combiner for combining the encoded signals for transmission via a single physical medium. A receiver for receiving and decoding the combined encoded signal contains filters for extracting the individual encoded signals and line decoders for decoding the individual encoded signals to generate the original digital data signals.

Abstract: The present invention provides a method for manufacturing a semiconductor device comprising a III-V semiconductor substrate, and an insulating layer deposited on the substrate by Atomic Layer Deposition (ALD). The use of ALD to deposit the insulating layer was found to facilitate the creation of active devices that avoid Fermi layer pinning. In addition, such insulating layer may be advantageously used as a passivation layer in III-V substrate based active devices and transistors.

Abstract: A centralized concentrator for use with a computer network and a method of distributing wireless communications in a computer network employing a distributed access system. In one embodiment, the centralized concentrator includes a wireless communicator and a central protocol processor. The wireless communicator sends and receives a wireless communication to a communications network and to a wireless client access subsystem. Coupled to the wireless communicator is the central protocol processor which provides bridge functionality for the wireless communication.

Abstract: A signal processing circuit and method in which a given signal, e.g., a receive data clock associated with a first chip and generated by a deserializer circuit, is synchronized with another signal, e.g., a clock signal from a second chip which is asynchronous with the receive data clock. The circuit may include first, second and third processing circuits, each of which performs a sampling function on a corresponding one of an early version, a middle version and a late version of the given signal, utilizing the clock signal to which the given signal is to be synchronized. A logic circuit coupled to outputs of each of the first, second and third processing circuits generates a control signal indicative of the presence or absence of a desired relationship, e.g., a desired phase relationship, between the clock signal and the first, second and third versions of the given signal. A selection circuit, e.g.

Abstract: The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. The problem of interconnection congestion is overcome by routing the interconnections through the substrate. The through interconnections are made by etching vias through the substrate by RIE, oxidizing the via sidewalls, and filling the vias with polysilicon.

Abstract: Speech recording is effected in a GSM phone handset (100) by storing in a memory (116) speech frames during the presence of speech, one or more SID frames during the absence of speech, and data representative of the duration of the absence of speech. In this way memory (116) does not store silent speech frames, and utilisation of memory space is therefore particularly efficient. In addition, items such as a voice activity detector and a comfort noise estimator, which are already provided in the handset as part of the GSM system, are “re-used” by the invention, thereby making efficient use of already-provided hardware/software.

Abstract: The digital-to-analog converter includes an output line, and a plurality of converters receiving control signals representative of digital data. Each converter selectively connects the output line to a voltage in response to a respective one of the control signals. Optionally, the digital-to-analog converter further includes a reset circuit for resetting the voltage on the output line to a reset voltage between portions of the analog waveform representing a digital data symbol.

Abstract: A method for reconstructing an aggregate stream of cells transmitted over communication links in an asynchronous transfer mode protocol includes determining a respective link delay for each of the communication links, including determining a fastest communication link. A common starting cell at which the cells from the communication links will correspond in time is determined based upon the fastest communication link. The method further includes filling a respective delay compensation buffer with corresponding cells for each of the communication links beginning with the common starting cell. The cells are read from the delay compensation buffers in a round-robin fashion to reconstruct the aggregate stream of cells.

Abstract: An article comprising a tunable filter includes an optical cavity, a tuning device and a filter-disabling device. The tuning device is operable to change the center transmission wavelength of the tunable filter. The filter-disabling device is operable to temporarily disrupt the finesse or otherwise affect the transmissibility of the optical cavity, thereby preventing the transmission of any intervening wavelengths during tuning.

Abstract: A method and apparatus are disclosed for reducing aliasing between neighboring subbands in cascaded filter banks. An alias reduction filter bank is included to reduce the aliasing components between different subbands. Generally, the magnitude response and phase of the alias reduction filter bank is similar to the magnitude response of the synthesis filter bank of the first stage filter bank. The alias reduction filter bank filters and adds the signals from a set of M2 subbands from the M1 subbands of the first stage analysis filter bank. A higher frequency resolution is obtained after the alias reduction stage by a following analysis filter bank. The signals of these subbands are first fed into an alias reduction filter bank to reduce the aliasing.

Abstract: A ferrite layer formation process that may be performed at a lower temperature than conventional ferrite formation processes. The formation process may produce highly anisotropic structures. A ferrite layer is deposited on a substrate while the substrate is exposed to a magnetic field. An intermediate layer may be positioned between the substrate and the ferrite to promote bonding of the ferrite to the substrate. The process may be performed at temperatures less than 300° C. Ferrite film anisotropy may be achieved by embodiments of the invention in the range of about 1000 dyn-cm/cm3 to about 2×106 dyn-cm/cm3.

Abstract: An electronic circuit includes a frequency conversion device (4), an oscillator (6), a band-pass filter (8), and a controller (14). The oscillator (6) is connected to the frequency conversion device (4), and the frequency conversion device (4) is connected to the band-pass filter (8). The frequency conversion device (4) is arranged to receive a first signal (S1) at a frequency (ft), and to transform the first signal (S1) into an intermediate frequency signal (S2) at an intermediate frequency (fi) by applying a selection frequency (floc) from the oscillator (6). The band-pass filter (8) is arranged to receive the intermediate signal (S2) and to perform a band-pass filtering at a centre frequency (fbpf) and with a bandwidth (fw), the centre frequency (fbpf) being equal to the intermediate frequency (fi) at a predetermined working temperature of the band-pass filter (8).

Abstract: The present invention is directed to a channel calibrator and a method of calibrating in-phase and quadrature phase channels for use with a quadrature mixing receiver. In one embodiment, the channel calibrator includes a balancer and an equalizer. The balancer reduces frequency dependent imbalance between an in-phase channel and a quadrature phase channel associated with the receiver. The equalizer decreases frequency independent mismatch between the in-phase channel and the quadrature phase channel.

Abstract: The present invention provides a method of manufacturing an antenna structure. In one embodiment, the method includes forming an antenna trace on a substrate proximate a ground plane of the substrate. In addition, the method includes creating an insulation region extending through the substrate and located between the antenna trace and the ground plane.

Abstract: The present invention provides methods of manufacturing and integrating optical devices. In one embodiment, a method of integrating an optical device may include forming a first device over a substrate, and forming a second device over the substrate and adjacent the first device with a deposition gas having an etchant selective to a deposited component of the deposition gas.

Abstract: A system and method of metrology (10) whereby a three dimensional shape profile is defined (16) for a surface feature on a substrate by applying (38) a transform function F(x) to an image intensity map I(x,y) obtained (40) by inspecting the substrate with a scanning electron microscope (12). The transform function F(x) is developed (34) by correlating the image intensity map of a first wafer (18) to a height vector (32) obtained by inspecting the first wafer with a more accurate metrology tool, for example a stylus nanoprofilometer (14). A simple ratio-based transform may be used to develop F(x). An asymmetric multiple parameter characterization of the three dimensional shape profile may be developed (74) by plotting critical space and width dimensions (SL, SR, W1, WR) from a vertical axis (C—C) as a function of height of the feature.

Abstract: A method for testing integrated circuits, including measuring a current signature delta value of a device under test and comparing the current signature delta value to a threshold current signature delta value to determine whether the current signature delta value is greater than the threshold current signature delta value. If the current signature delta value exceeds the threshold current signature delta value, the integrated circuit is rejected. Integrated circuits are also rejected if the post-stress current signature value exceeds a maximum current signature value, even though the current signature delta value is less than the threshold current signature delta value. In addition, an apparatus for testing integrated circuits is disclosed.

Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.

Abstract: A repetitive transmission technique with time diversity which provides improved signal-to-noise ratio (SNR) in the presence of packet loss. Time shifts are introduced between N versions of a particular block of information to be transmitted, and the time-shifted versions are encoded in a set of N encoders and transmitted as N packets. The time shift introduced between a given pair of the N versions corresponds to approximately 1/N of the time duration of a particular one of the versions. The SNR of a composite reconstructed signal generated from the N packets with the introduced time shift in a receiver of the system is approximately the same as would be obtained using a set of N independent encoders to generate the plurality of packets without the introduced time shifts. The gain in the SNR of the composite reconstructed signal attributable to the introduction of the time shifts is 10 log10N′, where N′=1, . . .

Abstract: The furniture piece facilitating wireless Local Area Network (LAN) access has a work surface and at least one support supporting the work surface. An antenna is disposed in one of the work surface and the support, and an access point is disposed in one of the work surface and the support.