Abstract: A process of interacting with a memory module to restore data backed up from volatile memory to nonvolatile memory of the memory module involves a host system configuring the volatile memory of the module to interoperate with a host memory controller via a DIMM memory interface to the module; the host configuring a controller of the module to copy data from the nonvolatile memory to a peripheral I/O bus, the configuration of the controller of the module carried out via the peripheral I/O bus; a host I/O controller receiving the data copied to the peripheral I/O bus and communicating the received data to a host memory controller; and the host memory controller copying the received data to the volatile memory via the DIMM memory interface, thus completing a restore of the data from nonvolatile memory to the volatile memory.

Abstract: “A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A non-volatile memory module includes a volatile memory circuit and a reference voltage generator coupled to supply a reference voltage to the volatile memory circuit. The reference voltage provides a level by which the volatile memory and external devices may communicate reliably at high speeds. The reference voltage is applied to an external interface of the non-volatile memory module through an isolation circuit. A control circuit coupled to the isolation interface and to a circuit which is adapted to detect when the non-volatile memory module no longer draws power from an external source.

Abstract: A memory module interfaces with a host system as a Dual Inline Memory Module (DIMM). The memory module includes a volatile memory and a nonvolatile memory, and provides a DIMM module interface to the volatile memory. A peripheral I/O bus interfaces to the nonvolatile memory, the peripheral I/O bus interface also interfaces to control logic of the memory module to initiate data backup from the volatile to the nonvolatile memory.

Abstract: “A circuit includes a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage receives charge current via a common charging terminal. A controller is configured to separately measure a stored potential of each capacitor stage in the series arrangement. The circuit includes logic to selectively remove a controlled amount of charge from each capacitor stage individually (discharge logic), and logic to operate the discharge logic to maintain each capacitor stage in the series arrangement at a substantially equal stored potential (balancing logic).

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's stored potential is created above an upper predetermined operating potential of the capacitor. Measurements of a capacitor's output voltage are obtained during the transient elevation of the capacitor's stored potential. A capacitance of the capacitor is determined from the measurements.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem includes a volatile memory and a nonvolatile memory. A controller includes logic to interface the volatile memory to an external system, so that the volatile memory is addressable for reading and writing by the external system. The controller includes logic to back up data from the volatile memory to the nonvolatile memory upon receiving a backup signal from the external system. A power controller includes logic to detect when power from the external system fails, and when power from the external system fails, to provide backup power for long enough to enable the controller to back up data from the volatile memory to a first region of the nonvolatile memory. The controller, upon receiving the backup signal from the external system, backs up data from the volatile memory to a second region of the nonvolatile memory different that the first region used to back up data from the volatile memory to the nonvolatile memory when power from the external system fails.

Abstract: A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.

Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.

Abstract: A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

Abstract: A non-volatile memory module includes a volatile memory circuit and a reference voltage generator coupled to supply a reference voltage to the volatile memory circuit. The reference voltage provides a level by which the volatile memory and external devices may communicate reliably at high speeds. The reference voltage is applied to an external interface of the non-volatile memory module through an isolation circuit. A control circuit coupled to the isolation interface and to a circuit which is adapted to detect when the non-volatile memory module no longer draws power from an external source.

Abstract: An apparatus includes a capacitor and logic to adjust an operating temperature of the capacitor according to a charge on the capacitor, and/or to adjust a charge of the capacitor according to the operating temperature of the capacitor to improve the useful life of the capacitor and increase its reliability.

Abstract: A memory system includes logic to distribute bits of a data word from a first memory across multiple pages of a flash memory.

Abstract: A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.

Abstract: A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear.

Abstract: A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.