Abstract: A photonic crystal waveguide apparatus has a photonic crystal having a waveguide which is capable of transmitting light having a frequency within a bandgap of the photonic crystal, and a resonant stub connected to the waveguide to control light in the waveguide. The resonant stub has a resonator region and a connecting channel which connects the resonator region to the waveguide. The resonant stub controls light transmission characteristics of the waveguide by creating a transmission zero in the transmission band of the waveguide. A tuner for tuning the resonant stub may also be provided to control the transmission zero to provide an active optical apparatus such as an on/off switch or a modulator.

Abstract: A signal analyzer has a display with two regions. In a first region there is displayed a first waveform representing a signal. The first waveform is shown in two dimensions. One dimension represents signal amplitude and one dimension represents signal frequency. In a second region is displayed a second waveform. The second waveform represents a subset of data points of the first waveform. The second waveform also is shown in two dimensions. One dimension represents signal amplitude and one dimension represents signal frequency.

Abstract: A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.

Abstract: The data path into a post decode mechanism is altered to allow post decode to process data before or as that data is placed into a destination memory structure in interior test memory. Other data will continue to be first placed into a memory structure in interior test memory before being applied to the post decode mechanism. Extensive masking capability coupled with copies of error tables allow incremental post decode analysis for a new test, and avoids counting of errors in locations that are already known to have failed during previous tests. Both errors within words and bit errors can be accumulated. The post decode mechanism is often capable of producing multiple type of results from a single pass through the data, whether applied on the fly or from a structure in interior test memory. The post decode mechanism has counters that count down from pre-loaded values representing thresholds for deciding something about error activity. A counts of zero produces a terminal count flag.

Abstract: Heterodyne based optical spectrum analysis (OSA) involves mixing an input signal with a swept local oscillator signal to generate a heterodyne beat signal and then stretching the heterodyne beat signal before the signal is sampled. A system for optical spectrum analysis includes a local oscillator source, an optical coupler, a heterodyne receiver, and a processor. A circuit for stretching the heterodyne beat signal is included in the heterodyne receiver and may include a diode in series with a capacitor and a resistor or a diode in series with a capacitor and a switch. Stretching the heterodyne beat signal involves extending the duration of the signal so that the signal can be detected with fewer samples per unit of time than an unstretched signal. Another embodiment of an OSA includes a first data acquisition unit for obtaining low resolution data and a second data acquisition unit for obtaining high resolution data.

Abstract: A polarization control device, comprising: a liquid crystal device containing a liquid crystal material with an optical anisostropy with substantially homeotropically aligned molecules when in a neutral electrical field state; a plurality of electrodes for applying an electrical field to change an orientation of the molecules of the liquid crystal material from their alignment in the neutral electrical filed state; a circuit for applying a voltage to the electrodes; and an optical system for directing light through the liquid crystal material.

Abstract: The invention is a communication system having a series of output modules that provide continuous synchronization output signals. Each output module has a driver assembly that has a driver output and a backup selector output that is capable of driving a failed next driver assembly. The driver output and the backup selector output can be different types. A sensor detects the failure of the driver or a backup driver output and generates a select signal in the failure state. A selector receives the driver output, the backup driver output, the select signal, and a select signal from the next driver assembly. The selector normally selects the driver output, but in response to a failure state from the select signal, isolates the failed driver output. The previous driver assembly transmits a backup selector output to the failed driver assembly to maintain a continuous driver output. The transformers are preferably placed on a separate card to reduce the thermal degradation of nearby electronics.

Abstract: Phase detector constructed from a plurality of multi-input gates which combine combinations of unretimed input data with retimed data and with clock signals to achieve output pulses proportional to the phase difference between the unretimed data and the clock. In the embodiment the phase detector comprises an input for receiving data signals; an input for receiving clock signals; an output for providing phase control signals; data retiming circuitry for accepting unretimed data signals from said data input and for providing even and odd retimed signals therefrom; a plurality of multi-input gates having inputs connected to different combinations of said unretimed data signals, said retimed data signals, and said clock signals, such that no said gate can be active in two consecutive UIs, when a UI is defined as the length of time allocated to a single bit; and a combiner for mixing the outputs of at least two of said gates.

Abstract: An apparatus for automatically accumulating and storing information has a destination memory and an indexing circuit. The indexing circuit has an input port, a selector having a selector output, a register holding a value from the selector output and presenting the selector output value at a register output, and an accumulator accepting a value from the input port and a value from the register output and presenting a sum of the input port and register output values at an accumulator output. The selector receives the input port value from the input port, the accumulator output, and the value from the register output, the selector output being based upon a programmable selection code. The register output is connected to the destination memory .

Abstract: A distributed control system includes a transducer having an electronic data sheet that enables it to be accessed via a variety of differing types of field-bus networks. The electronic data sheet stores a set of object information corresponding to a set of differing object models associated with the differing types of field-bus networks. The distributed control system includes a component node which couples to a particular one of the differing types of field-bus networks and which couples to the transducer through a standard interface. The component node translates between the particular one of the object models and the standard interface during an access of the transducer that originates on the particular one of the differing types of field-bus networks.

Abstract: Systems and methods of converting data streams from one clocking domain to another are described. In one aspect, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle at an average rate RIN, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at an average rate ROUT, wherein M has an integer value of at least 1 and M≠N.

Abstract: A positioning device for determining the position of an object includes an anchoring surface, a first movable carriage on which the object is loaded and which has a means for suctioning onto the anchoring surface, a second movable carriage which has a drive assembly and which is connected with the first movable carriage as needed, and a connecting means which controls the connection of the first and second movable carriages. The first and second movable carriages are connected by the drive assembly and the first movable carriage is conveyed to a predetermined position on the anchoring surface and is suctioned and anchored on the anchoring surface at this position by a means for breaking the connection between the first and second movable carriages and for performing the suctioning to position the object.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: A first system includes a converter, complex signal generator, exponentiator, FFT module and processor to estimate carrier frequency of a high symbol rate quadrature amplutide modulated (QAM) signal relative to a target carrier frequency. The converter converts the applied QAM signal to an intermediate frequency (IF) signal and digitizes the IF signal at a predesignated sample rate. The complex signal generator extracts a real component of the digitized IF signal, provides an imaginary component of the digitized IF signal and then combines the real component and the imaginary component in a complex signal. The exponentiator, raises the complex signal to a predesignated power and the FFT module performs a Fast Fourier Transform (FFT), having a predetermined number of samples, on the complex signal as raised to the predesignated power.

Abstract: A digital image capture system includes an image sensor package and a powered lens element that is attached to the image sensor package. The image sensor package includes an image sensor, a package structure for holding the image sensor, and electrical connectors for creating electrical connection between the image sensor and a circuit board. The package structure and the powered lens element include complementary surfaces that enable the powered lens element to be attached to the image sensor package. Preferably, the powered lens element is glued to the package structure to create a sealed environment for the image sensor. In an embodiment, a temporary protective cover is attached to the powered lens element to protect the powered lens element during attachment of the image sensor package to the circuit board. In an embodiment of the digital image capture system, an additional powered lens element is attached to the powered lens element to create a composite lens element.

Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by adjusting the source resistance of the pre-drive devices to generate a slew-controlled pre-drive signal for driving the output drive devices.

Abstract: An encoder that includes a sensing device that senses encoding marks on a sensing surface that also includes one or more reference marks. The sensing device generates first and second encoder signals when the encoding marks pass the sensing device. The encoding signals define the direction of motion and degree of movement of the sensing surface. A register stores the position of the encoding surface relative to the sensing device. A controller receives the first and second encoder signals and increments or decrements the digital register based on the received first and second encoder signals. The encoder also includes a reference mark detector that generates a first reference mark signal when the first reference mark passes the reference mark detector. The controller resets the digital value to a first reference value when the encoder receives the first reference mark signal.

Abstract: A method is disclosed by which precision alignment of optical fiber to wave-guide or other optical elements can be carried out with an adjustable microstructure in active alignment mode fiber attachment. A microstructure containing three elongated U-grooves can be combined effectively to produce a movable and adjustable V-groove structure, which can be used to achieve sub-micron scale alignment control with zero rotational torque. This device not only makes fiber alignment easy and fast but also maintains the fiber attachment position after alignment and epoxy bonding. Multiple fiber array alignment can be carried out with only a global alignment of two end fibers.

Abstract: The present invention concerns a device for positioning an object, consisting of a holder with a holding cup into which the object can be inserted in radial direction, wherein a rotation device is provided, which acts together with the object when the object is inserted in the holding cup and which allows for a rotational adjustment of the object around its longitudinal axis and relative to the holding cup. On the object, there is a drive component in the form of at least one radial ledge and/or at least one radial indentation into which the rotation device reaches when performing a rotational adjustment of the object.

Abstract: A memory controller comprises a programmable interface coupled to address circuitry. The programmable interface receives a configuration signal into the memory controller indicating a selected address configuration. The address circuitry processes system addresses based on the selected address configuration to generate memory addresses. The configuration signal may also indicate a selected memory configuration, and the address circuitry processes the system addresses based on the selected memory configuration to generate memory device selections.