Patents Assigned to Agilent Technologies
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Patent number: 6865496Abstract: A sampling apparatus for use in high data rate jitter measurement systems based on offset sampling uses a trigger circuit, along with a time-based variable delay, to align a sampling strobe to drive two samplers. An input data signal is split and fed via separate signal paths into the two samplers. One of the samplers is delayed in sampling the input signal or the input is delayed to one of the samplers, such that the two samples of the input signal are offset in time. The jitter present in the SUT can be calculated using the two samples. In addition, when using two strobe circuits, the jitter inherently present in the strobe circuits can be compensated for by offset sampling a reference clock with each main strobe to determine the phase and cycle number of the reference clock at each strobe time.Type: GrantFiled: November 1, 2001Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Lovell H. Camnitz, Roger L. Jungerman, Randall King
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Patent number: 6864761Abstract: A distributed capacitive/resistive electronic device. An electronic device is described which includes a dielectric substrate, a first resistive component, a second resistive component, and a connecting component. The first resistive component is affixed to a first side of the dielectric substrate. The second resistive component is affixed to a second side of the dielectric substrate, wherein the second side is oppositely located from the first side. The connecting component is affixed to the dielectric substrate, wherein the connecting component electrically connects the first resistive component to the second resistive component, wherein the connecting component is electrically connectable to other electronic circuitry, and wherein, at a location removed from the connecting component, the second resistive component is electrically connectable to other electronic circuitry.Type: GrantFiled: October 22, 2002Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: David D. Eskeldson, Martin L Guth
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Patent number: 6864694Abstract: A voltage probe includes a signal lead that is configured to be soldered to a probing location in a device that is to be probed by the voltage probe, and a first cable that is coupled to the signal lead and that is configured to conduct an output signal that is responsive to an input signal that is received by the signal lead from the device. The signal lead has a thermal conductivity of less than 200 Watts per meter Kelvin (W/mK). Methods and other systems for providing electrical connections to devices under test are disclosed.Type: GrantFiled: October 31, 2002Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventor: Michael Thomas McTigue
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Patent number: 6865704Abstract: Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.Type: GrantFiled: November 9, 2001Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Stuart L. Whannel, Garrett O'Brien, John Stephen Walther
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Patent number: 6865345Abstract: A frequency translating device (FTD) includes at least one light-activated resistor (LAR) connected to down-convert a radio frequency (RF) to an intermediate frequency (IF) and to up-convert an IF to an RF and a source of modulated light that is optically connected to the LAR. The source of modulated light is modulated in response to a local oscillator (LO) and the LAR is activated in response to the modulated light. Modulated light can be generated from a light source and an LO by, for example, directly modulating the light source, modulating a transmission switch that blocks the transmission of light to the LAR, or modulating a light path switch. The LAR-based FTD can be used as a reciprocal FTD to characterize another FTD in a three-pair measurement system. An FTD may include more than one LAR to form, for example, single-balanced and double-balanced LAR-based FTDs.Type: GrantFiled: August 28, 2001Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventor: Richard K. Karlquist
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Patent number: 6864689Abstract: Attenuation of a pulsed signal traversing a cable is assessed by identifying a pulse in a signal received after traversing the cable and determining first and second reference signal levels in dependence upon characteristics of the pulse. A measurement is made of the slope of the pulse between the first and second reference signal levels (such as 25% and 75% of the peak pulse magnitude), and this measurement is used to determine an indication of the cable attenuation. The cable attenuation may in turn be used to determine a threshold for indicating loss of signal during a measurement operation.Type: GrantFiled: January 9, 2003Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Alexander Stephen, Daya Rasaratnam, Colin Johnstone
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Patent number: 6864699Abstract: An apparatus for testing digital and analog signals from an integrated circuit includes an adder or subtractor 17 for being supplied with an analog signal outputted from the integrated circuit of a device under test and a signal outputted from a driver 11, an integrator 14 for being supplied with an analog signal outputted from the adder or subtractor 17, a switch 22 for selectively transmitting an analog signal outputted from the integrator 14 and a digital signal outputted from the integrated circuit to the comparator 13, and a switch 24 for selectively transmitting a signal outputted from a memory 20 and a signal outputted from a comparator 13 to the driver 11. At least one of the switches 22, 24 is operated depending on whether a signal to be tested is analog or digital.Type: GrantFiled: March 24, 2004Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Hiroshi Sakayori, Takanori Komuro
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Patent number: 6865321Abstract: The present invention involves the use of coupling fixtures that permit optical elements to be aligned with planar waveguides of planar lightwave circuits. In particular, alignment of the coupling fixtures typically does not require powering of the optical element yet provides a degree of alignment that is comparable to that obtained by active alignment techniques. The alignment process is accompanied by an assembly process that may be performed at relatively high temperatures. This typically makes it possible to use solder for attaching the optical element to the planar lightwave circuit while retaining alignment accuracy. This is advantageous since soldering typically is the preferred choice for assembling components, such as single-mode devices, that require a relatively high degree of alignment precision together with good mechanical rigidity.Type: GrantFiled: July 31, 2002Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Richard Paul Tella, William Gong, Brian Lemoff
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Patent number: 6864110Abstract: The present invention provides a process and apparatus for selectively depositing materials on a semiconductor device, such as depositing phosphors or other optical materials on a light emitting diode (LED), using an electrophoretic deposition process. The semiconductor device comprises a p-side and an n-side. A first biasing voltage is applied between an anode and the p-side of the semiconductor device. A second biasing voltage is applied between the p-side and the n-side of the semiconductor device. The relative biasing of the p-side and the n-side determines where coating is deposited on the semiconductor device. An optional pre-coating process is used to deposit a high resistivity dielectric material, such as silica, on the semiconductor device. The pre-coating can even the electric field on the surface of the semiconductor device, where local features such as metal connections or passivation layers disturb the electric field during phosphor deposition without pre-coating.Type: GrantFiled: October 22, 2002Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Christopher J. Summers, Hisham Menkara, Bee Yin Janet Chua
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Patent number: 6864696Abstract: A probe that connects test and measurement equipment to a device under test via a plurality of cables. The probe is formed of a plurality of printed circuit boards that are stacked together. Each board is connected to one of the plurality of cables and has a longitudinal set of pads along an edge electrically connected to the cable. The stacked plurality of printed circuit boards form a two dimensional array of pads for connecting to a similar set of pads on a device under test.Type: GrantFiled: October 31, 2002Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Donald M. Logelin, Bob J. Self, Robert H. Wardwell
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Patent number: 6865706Abstract: The present invention is generally directed to an improved automatic test pattern generator for generating test patterns that are used by an integrated circuit testing device. In accordance with one aspect of the invention, a method is provided for generating a set of test vectors for testing an integrated circuit, each test vector of the set of test vectors containing a plurality of bits defining test inputs for the integrated circuit. The method includes the steps of defining a list of faults for the integrated circuit, and generating at least one test vector that defines values for those inputs necessary to detect at least one target fault selected from the list of faults, the values comprising only a portion of the bits of the at least one test vector, wherein a remainder of the bits in the at least one test vector are unspecified bit positions. The method further includes the step of setting the values of a plurality of the unspecified bit positions using a non-random filling methodology.Type: GrantFiled: June 7, 2000Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: John G Rohrbaugh, Jeff Rearick
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Patent number: 6865037Abstract: Systems and methods for adjusting optical path length of an optical path are provided. The systems and methods can be used to controllably adjust optical path length in an external cavity laser. A representative optical path having a first end and a second end comprises a first transparent refractive element located in the optical path between the first end and the second end. The transparent refractive element is adjustable to adjust the optical path length of the optical path without changing the physical distance between the first end and the second end. A representative method includes introducing a transparent refractive element into the optical path and adjusting the transparent refractive element to change the optical path length without changing the physical distance between the first end and the second end of the optical path.Type: GrantFiled: October 17, 2002Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Dennis Carlo Diaz, Geraint Owen, Susan Hunter, George M. Clifford, Jr.
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Patent number: 6864097Abstract: A method of reading an array of moieties such as polynucleotides (for example, DNA) on at least a portion of a surface of a transparent slide which is opposite a first portion on the opposing surface, which array has been previously exposed to a sample. The method may include mounting the slide on a slide holder and retaining the slide thereon in a mounted position in which the holder does not contact the previously exposed array. The holder is then inserted into an array reader and the array read. A holder and slides which can be used in the method are also provided.Type: GrantFiled: September 27, 2000Date of Patent: March 8, 2005Assignee: Agilent Technologies, Inc.Inventors: Carol T. Schembri, Kimberly L. Tam
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Patent number: 6860419Abstract: An apparatus and method for controlling movement of packaged devices. Specifically, embodiments of the present invention discloses an apparatus a method of providing a controlling mechanism for effecting physical control over a device that is disposed on a structure. An exothermically reactive structure is disposed on the controlling mechanism, such that, when activated, an exothermic alloying reaction between alloys in the exothermically reactive structure operates the controlling mechanism. The controlling mechanism is adapted to release the device, position the device, or tune the device.Type: GrantFiled: August 30, 2002Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventor: Jonathan Simon
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Patent number: 6860620Abstract: A light unit is provided that includes a thin flexible substrate layer. A number of flexible electrical tracks are formed on the flexible substrate layer. A number of Light Emitting Diodes (LEDs) are arranged on the flexible substrate layer along the electrical tracks and are electrically connected to the electrical tracks such that the light unit is both thin and flexible.Type: GrantFiled: May 9, 2003Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventors: Yew Cheong Kuan, Seong Choon Lim, Kar Phooi Foong, Wen Ya Ou
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Patent number: 6861669Abstract: A compound display for presenting images to a viewer is disclosed. The compound display includes first and second displays positioned such that the first display is viewable through the second display when the second display is not generating an image. The first display displays a first image. The second display includes an OLED having a first state in which the OLED generates light of a first intensity and a second state in which the OLED does not generate light. The OLED is transparent to light from the first display when the OLED is not generating light. The second display is positioned between the first display and the viewer. In one embodiment, the first display includes an array of inorganic LEDs that generate light of a greater intensity than that generated by said OLED in said first state.Type: GrantFiled: March 31, 2003Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventors: Boon Chun Tan, Justin Lim Hwa Aik
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Patent number: 6861733Abstract: A clamp member or device includes a clamping portion with a rigid portion from which extend a number of independently flexible clamp fingers for contacting and clamping lead frame leads. The flexible clamp fingers have pivot points for pivoting about. The pivot points are provided integrally with the rigid portion of the clamping portion so that the fingers can flex independently of each other. The member is made from a single piece of machined steel.Type: GrantFiled: January 22, 2003Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventor: Theng-Hui Kek
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Patent number: 6861846Abstract: A distortion measurement method uses alternative measurements to determine the distortion of a DUT, depending on the ratio of the distortion at an output of the DUT to distortion of a source stimulating the DUT. The method includes calibrating the VNA at a distortion frequency, measuring a first gain of the DUT with the source and the receivers of the VNA set to the distortion frequency, and measuring a second gain of the DUT with the source of the VNA set to a fundamental frequency and the receivers of the VNA set to the distortion frequency. When the second gain is less than a predesignated threshold, a match-corrected source signal is acquired and used with the first gain and the second gain to determine the distortion of the DUT. When the second gain is not less than the predesignated threshold, a match-corrected DUT output signal is measured and used with the first gain and the second gain to determine the distortion of the DUT.Type: GrantFiled: December 16, 2002Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventor: Keith Frederick Anderson
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Patent number: 6862701Abstract: Self testing of a data communication system that includes a presettable scrambler and a complementary presettable descrambler is performed by presetting the presettable scrambler to a preset state. A seed payload field is scrambled using the presettable scrambler to generate fields of a test sequence. The fields of the test sequence are transmitted and corresponding received test sequence fields are received. The received test sequence fields are descrambled using the presettable descrambler to generate respective recovered test sequence fields. Differences between the recovered test sequence fields and the seed payload field are then detected as errors. In an embodiment, the seed payload field and the preset state of the presettable scrambler are chosen to generate a test sequence that imposes a known stress, such as a given run length, to the data communication system.Type: GrantFiled: March 6, 2001Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventors: Richard C. Walker, Patricia A. Thaler
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Patent number: 6862377Abstract: Methods and systems allow an in situ determination of the magnitude of PMD in an optical network and provide an estimate of the PMD impairment in the transmitted signal even when PMD is time dependent.Type: GrantFiled: October 15, 2002Date of Patent: March 1, 2005Assignee: Agilent Technologies, Inc.Inventors: Bogdan Szafraniec, Douglas M. Baney