Abstract: A method for playing a fast rolling music disc is provided. A music disc is read at an accelerated rate and played at a standard rate by discretely buffering data blocks into a ping pong buffer. Playing of a first data block stored in the first buffer, and buffering of a second data block into the second buffer are concurrently executed. When the playing of the first data block is concluded, the playing order of the first buffer and the second buffer are interchanged, and the concurrent playing and buffering step is repeated. Such that the second data block is played in the second buffer while a third data block is buffered into the first buffer. Discreteness between the second data block and the first data block is dependent on a skipping ratio, and the skipping ratio is dependent on the accelerated rate.

Abstract: Methods that include using a noble gas ion beam to determine dopant information for a sample are disclosed, the dopant information including dopant concentration in the sample, dopant location in the sample, or both.

Abstract: Ion sources, systems and methods are disclosed.

Abstract: Ion sources, systems and methods are disclosed.

Abstract: A signal generating circuit includes a detecting circuit, a charge pump, a first level shifter, a filtering circuit, a second level shifter and a controllable oscillator. The detecting circuit outputs a detecting signal according to a reference signal and an oscillating signal. The charge pump outputs a first output signal by performing a charging or discharging operation according to the detecting signal. The first level shifter adjusts a voltage level of the first output signal to thereby output a second output signal. The filtering circuit generates a first filtered control signal according to the second output signal. The second level shifter adjusts a voltage level of the first filtered controlling signal to output a second filtered control signal. The controllable oscillator outputs the oscillating signal according to the second filtered control signal.

Abstract: A digital-to-analog converting system with sampling rate conversions includes an interpolator, S orders of operating and filtering units, an up-converting and down-converting circuit, and a signal processing circuit. The interpolator performs an N-times interpolation on a first digital input signal to generate a second digital input signal. Each order of the operating and filtering unit includes a K-times zero-padding circuit and a filtering circuit. The filtering circuit performs a filtering operation to generate a filtered digital input signal. The up-converting and down-converting circuit performs a B-times up-conversion and an A-times down-conversion on the filtered digital input signal to generate a fourth digital input signal. The signal processing circuit generates an analog output signal according to the fourth digital input signal.

Abstract: Ion sources, systems and methods are disclosed.

Abstract: An ESD/EOS protection circuit includes a first protection circuit and a second protection circuit. The first protection circuit is coupled between an I/O pad and a power pad and includes a first P-type transistor. The P-type transistor includes a control node, a floating gate, a first connection node, and a second connection node, wherein the first connection node of the first P-type transistor is coupled to the power pad and the second connection node of the first P-type transistor is coupled to the I/O pad. The second protection circuit is coupled between the I/O pad and a ground pad.

Abstract: An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory.

Abstract: A phase locked loop device is provided. The phase locked loop device includes a phase/frequency detector, a charge pump, a low pass filter, a voltage-controlled oscillator, and a control unit. The phase/frequency detector generates a compared signal corresponding to a phase difference between a reference clock signal and a feedback clock signal. The charge pump coupled to the phase/frequency detector generates a pump current according to the compared signal. The low pass filter coupled to the charge pump generates an operating voltage corresponding to the pump current. The voltage-controlled oscillator coupled to the low pass filter generates an output clock signal in response to the operating voltage. The control unit coupled to the low pass filter and the voltage-controlled oscillator constrains the operating voltage to a predetermined voltage level when the frequency of the output clock signal is out of a predetermined frequency range.

Abstract: A data protection method is provided. The data protection method is adapted for a plurality of pages of a plurality of blocks in a memory. The data protection method records bit error weight values and erasing times of the blocks during routine operations of the memory. Therefore, when the system is in an idle status, the data of those blocks having higher bit error weight values can be recovered. Further, the data protection method moves data of those blocks having less erasing times to other blocks, so as to release the blocks having less erasing times from the data area for use. Then, the data protection method utilizes all blocks of the non-volatile memory in an average manner, so as to effectively protect the data saved in the memory and average the erasing operations.

Abstract: Electronic devices with more than one video output terminals and capable of providing distinct videos at different video output terminals. The electronic device comprises first and second display processors driving first and second video output terminals, respectively. The first display processor comprises a blender and a multiplexer. The blender blends a video with image signals, provides a fully-blended video for the first video output terminal, outputs the video, the partly-blended videos and the fully-blended video to the multiplexer. The second display processor is coupled between the output terminal of the multiplexer and the second video output terminal.

Abstract: An adjusting method for a smart antenna is provided. The adjusting method divides all possible reading directions of the smart antenna into a plurality of scanning directions and a plurality of idle directions by a first form. In searching for the optimal parameters of each of a plurality of communication channels, the adjusting method firstly adjusts the reading direction according to the plurality of scanning directions, and then adjusts the reading direction according to the plurality of idle directions. Further, the first form remain updated in accordance the process of searching for the optimal parameters of each of the communication channels, thus effectively saving the time spent on the full frequency scanning process. Further, the optimal parameters of each of the communication channels are recorded in a second form, so that the smart antenna is regulated according to the second form.

Abstract: A digital to analog converter (DAC) converting a digital code to an output voltage and capable of self calibration. The DAC includes a self-calibration signal generator generating a self-calibration signal based on the output voltage, a constant current generator, a first and a second current provider and a current-voltage converter. The current generating elements of the first and second current providers provide proportional currents, and are enabled/disabled according to the self-calibration signal and the digital code, respectively. The constant current is divided into the actual working current generating elements of the first current provider, and an output current is generated by the actual working current generating elements of the second current provider. The output current is converted to the output voltage by the current-voltage converter.

Abstract: A fine symbol timing synchronization method and apparatus in an orthogonal frequency-division multiplexing (OFDM) system are provided. The fine symbol timing synchronization method finds a path with a minimum mean square error (MMSE) as a first path among a plurality of paths, and a formula of the mean square error (MSE) used by the method is a simplified formula of the original MSE formula with low calculation complexity. Therefore, the time required by the fine symbol timing synchronization method is short, and a correct first path can be found, so as to lock a starting position of a fast Fourier transform (FFT) window on a starting position of a symbol signal of the correct first path.

Abstract: A DC/DC converter includes a converting circuit for converting a first voltage into a second voltage; a controller for generating spread spectrum switching signals; and a switch according to the spread spectrum switching signals controlling the on/off state of the switch.

Abstract: Video processors and memory management methods thereof are provided, wherein the video processor is controlled by a central processing unit, and is coupled to a system memory to receive a macroblock. The video processor has two local memories, a control circuit and an image processing unit. The control circuit divides the macroblock into pixel segments, and disposes the pixel segments in the two local memories. The image processing unit accesses the two local memories for executing an image processing procedure. The system memory is refreshed by a processed macroblock in the two local memories.

Abstract: An auto gain controller (AGC) and a control method thereof are provided. An input signal is amplified by a radio frequency (RF) amplifier and an intermediate frequency (IF) amplifier. When strength of the input signal is lower than a threshold, a gain curve of the RF amplifier is lowered while a gain curve of the IF amplifier is raised. When the strength of the input signal is greater than the threshold, a takeover point (TOP) of the IF amplifier is changed from a first takeover point to a second takeover point.

Abstract: A signal processing circuit and a signal processing method for removing a co-channel interference from a digital signal are provided. The signal processing circuit employs an adaptive filter for estimating a co-channel interference in a received digital signal. The adaptive filter takes the digital signal having a symbol signal outputted from a slicer subtracted therefrom as an input thereof. As such, the output of the adaptive filter does not contain any symbol data. Therefore, when the outputted estimation signal is subtracted from the received digital signal, it won't introduce any inter-symbol interference.

Abstract: A generating method and a user interface apparatus of menu shortcuts are provided. The present method is used for generating a menu shortcut list corresponding to a hierarchical content menu including a plurality of function items. When one of the function items in the content menu is selected, a frequency parameter of the selected function item is calculated and determined whether larger than a threshold. If the frequency parameter is larger than the threshold, a prompt is performed to remind the user whether to add the function item to the menu shortcut list. Then, the function item is added to the menu shortcut list according to a selecting signal input by the user. Accordingly, a process for setting the menu shortcuts can be simplified.