Abstract: A timing lock identification method is provided according to an embodiment of the disclosure. The method includes: generating one or more first phase adjustment pulses and one or more second phase adjustment pulses by a timing recovery circuit, where the one or more first phase adjustment pulses are configured to increase a phase of an output signal of an oscillator, and the one or more second phase adjustment pulses are configured to decrease the phase of the output signal; and obtaining a difference value between the number of the one or more first phase adjustment pulses and the number of the one or more second phase adjustment pulses in a detection window and determining whether the timing recovery circuit reaches a locking state of timing recovery according to the difference value. Furthermore, a signal receiving circuit is provided according to an embodiment of the disclosure.

Abstract: An object recognition method and system thereof are provided. A recognition result of a first object of a (i?1)th frame of a video stream is obtained. A ith frame is received, and a second object is detected from the ith frame. Whether the first object and the second object are corresponding to the same target object is determined according to a position of the first object in the (i?1)th frame and a position of the second object in the ith frame. If the first object and the second object are corresponding to the same target object, whether a recognition confidence level is greater than a predetermined threshold is determined so as to perform the object recognition on the second object or assign the recognition result of the first object to the second object.

Abstract: A communication device and an echo cancellation method are provided. A digital echo canceller is coupled to a transmitting circuit and a receiving circuit to generate an echo energy indicator according to a digital output signal and a digital input signal. A transceiving front-end circuit receives the analog output signal and generates a hybrid interface signal. A hybrid fine-tune circuit generates a first and a second capacitance calibration signals according to the echo energy indicator. An analog echo cancellation circuit receives the first and second capacitance calibration signals, and includes a first and a second variable capacitors controlled by the first capacitance calibration signal and a third and a fourth variable capacitors controlled by the second capacitance calibration signal. The analog echo cancellation circuit receives the analog output signal and the hybrid interface signal, and generates the analog input signal according to the first and second capacitance calibration signals.

Abstract: The invention provides a circuit structure sharing the same memory, where the circuit structure includes a first volatile memory, a system chip and a signal processing chip. The system chip is connected to the first volatile memory via a first connection interface. The signal processing chip is connected to the system chip via a second connection interface. A memory controller is disposed in the system chip and connected to the first connection interface and the second connection interface. The signal processing chip transmits a first access command to the memory controller via the second connection interface, and the memory controller accesses the first volatile memory via the first connection interface according to the first access command and transmits the access result of the first access command to the signal processing chip via the second connection interface.

Abstract: A symbol synchronization method is provided according to an embodiment of the disclosure. The method includes: receiving an input signal which includes a plurality of symbols; performing a cross-correlation operation on a plurality of first samples of the input signal according to a known sequence of a first type symbol among the symbols to obtain a plurality of cross-correlation results; accumulating the cross-correlation results to obtain an ending position of the first type symbol; delaying a plurality of second samples of the input signal according to a length of a second type symbol among the symbols to perform an auto-correlation operation; and correcting the ending position according to an operation result of the auto-correlation operation. In addition, a corresponding signal receiving circuit is provided according to an embodiment of the disclosure.

Abstract: A signal receiving device and an equalizer tuning method thereof are provided. A first equalizer receives an input signal and generates a first equalized signal by compensating the input signal according to a first equalization parameter. A second equalizer generates a second equalized signal by compensating the first equalized signal according to a second equalization parameter. A clock and data recovery circuit recovers the second equalized signal to generate an output signal. An equalizing controller receives the input signal and outputs a first control signal and a second control signal, to adjust the first equalization parameter according to the first control signal and adjust the second equalization parameter according to the second control signal. The equalizing controller detects a first pattern symbol and a second pattern symbol from the output signal and tunes the second equalization parameter according to the number of the first pattern symbol and the second pattern symbol.

Abstract: A symbol synchronization method is provided according to an embodiment of the disclosure. The method includes: receiving an input signal which includes a plurality of symbols; performing a cross-correlation operation on a plurality of first samples of the input signal according to a known sequence of a first type symbol among the symbols to obtain a plurality of cross-correlation results; accumulating the cross-correlation results to obtain an ending position of the first type symbol; delaying a plurality of second samples of the input signal according to a length of a second type symbol among the symbols to perform an auto-correlation operation; and correcting the ending position according to an operation result of the auto-correlation operation. In addition, a corresponding signal receiving circuit is provided according to an embodiment of the disclosure.

Abstract: The disclosure provided a low noise block converter for converting RF signal received from a satellite into IF signal, where the image rejection of the RF signal is performed in two stages through a low noise amplifier (LNA) integrated circuit (IC). The disclosure reduced the number of discrete components by integrating electronic components onto one integrated circuit (or chip), and at the same, improves the noise figure of the LNB converter. The LNB IC comprises LNA circuits, RF path selector, and signal downconverter, where the image rejection is performed by a combination of the LNA circuits and the signal downconverter.

Abstract: A timing lock identification method is provided according to an embodiment of the disclosure. The method includes: generating one or more first phase adjustment pulses and one or more second phase adjustment pulses by a timing recovery circuit, where the one or more first phase adjustment pulses are configured to increase a phase of an output signal of an oscillator, and the one or more second phase adjustment pulses are configured to decrease the phase of the output signal; and obtaining a difference value between the number of the one or more first phase adjustment pulses and the number of the one or more second phase adjustment pulses in a detection window and determining whether the timing recovery circuit reaches a locking state of timing recovery according to the difference value. Furthermore, a signal receiving circuit is provided according to an embodiment of the disclosure.

Abstract: An overvoltage protection device including an output stage, a first switch and a first load providing circuit is provided. The output stage has a first input terminal to receive a first signal, and generates an output signal at an output terminal of the output stage according to the first signal. A first terminal of the first switch is coupled to the first input terminal of the output stage, and a control terminal of the first switch receives a second signal. The first signal is the delayed second signal. The first load providing circuit is coupled to a second terminal of the first switch. The first load providing circuit provides an impedance to the first input terminal when the first switch is turned on.

Abstract: An electrostatic discharge (ESD) protection device including an ESD protection unit and a control circuit is provided. When a voltage level of a signal received by a signal input terminal reaches an ESD protection level, the ESD protection unit transmits the signal from the signal input terminal to the system voltage terminal. The control circuit controls a conduction state between the signal input terminal and the system voltage terminal through the ESD protection unit. The control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the ESD protection unit, and to prevent the ESD protection unit from transmitting the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the ESD protection level.

Abstract: A system for optimum phase searching in an Ethernet physical layer includes a time recovering circuit and an equalizer. The time recovering circuit includes a loop filter and a time error detector, and the equalizer includes a feed forward equalizer, a slicer and a feed backward equalizer. An optimum phase searching method includes obtaining optimum phases when mean squared errors calculated by the slicer are less than a first threshold, absolute values of mean values of outputs calculated by a time error detector are less than a second threshold, and the outputs are monotonic.

Abstract: A communication device and an echo cancellation method are provided. A digital echo canceller is coupled to a transmitting circuit and a receiving circuit to generate an echo energy indicator according to a digital output signal and a digital input signal. A transceiving front-end circuit receives the analog output signal and generates a hybrid interface signal. A hybrid fine-tune circuit generates a first and a second capacitance calibration signals according to the echo energy indicator. An analog echo cancellation circuit receives the first and second capacitance calibration signals, and includes a first and a second variable capacitors controlled by the first capacitance calibration signal and a third and a fourth variable capacitors controlled by the second capacitance calibration signal. The analog echo cancellation circuit receives the analog output signal and the hybrid interface signal, and generates the analog input signal according to the first and second capacitance calibration signals.

Abstract: The embodiments of the disclosure introduce a novel receiver having a smart listening mode for reducing the current consumption of a receiver while waiting for a data packet. In the smart listening mode, the receiver temporarily disables one signal path of a quadrature signal (e.g., I or Q path) until the receiver detects an arrival of data packet via a second signal path of the quadrature signal. The receiver continuously monitors the enabled signal path for the incoming data packet via in-channel energy. After the incoming data packet is detected, it is further determined whether the incoming data packet is a valid data packet. If not, one of the signal paths would be disabled again. As a result, the current consumption of the receiver is reduced while waiting for an incoming data packet.

Abstract: A hybrid decoding method and a gigabit Ethernet receiver using the same are provided. The hybrid decoding method and the gigabit Ethernet receiver detect and determine error propagation due to burst interference in a currently used main P-tap parallel decision feedback decoder, decode an Ethernet data stream using a trellis coded modulation (TCM) decoder, and determine a follow-up main decoding algorithm according to the decoded results of the two decoders in the same time interval to effectively prevent error propagation due to burst interference.

Abstract: A capacitor array structure which includes N capacitor units is provided. Each capacitor unit includes a first metal layer, a second metal layer, and a third metal layer to form an upper electrode and a lower electrode. The second metal layer is disposed between the first metal layer and the third metal layer, and includes a second patterned metal portion of the lower electrode and a first patterned metal portion of the upper electrode. disposed above. The second patterned metal portion of the lower electrode has an opening, and a side of the first patterned metal portion of the upper electrode is exposed in the opening, such that the side of the first patterned metal portion of the upper electrode is adjacent to the lower electrode of another capacitor unit.

Abstract: A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.

Abstract: The disclosure provided a tuner circuit having a zero power loop through (ZPLT) circuit that is capable of providing a loop through path even when no power is being supplied or without a standalone power supply. The tuner circuit includes an input terminal, an output terminal, a ZPLT circuit, and an internal resistor. The input terminal receives a radio frequency (RF) signal. The output terminal is connected to a subsequent tuner. The ZPLT is connected between the input terminal and the output terminal. The internal and an external resistor connected between the turner circuit and subsequent tuner form a voltage divider to divide a bias found at the output terminal to enable the ZPLT circuit for providing a loop through path to deliver the RF signal to the output terminal when the tuner circuit is not powered by a standalone power or a low noise amplifier is enabled.

Abstract: An output stage circuit including an amplifier, a switching circuit and a selection circuit is provided. The amplifier converts an input signal into an output signal. The switching circuit is coupled between an output terminal of the amplifier and ground. The selection circuit includes a first-mode-selection-unit and a second-mode-selection unit. The first control signal is selected as a switching signal by the first-mode-selection unit when a power-detection signal is in a high level, so that the switching circuit is selectively turned on. The switching circuit is turned on according to a voltage stored in a storage capacitor of the second-mode-selection unit when the power-detection signal is in a low level, so that the output terminal of the amplifier is coupled to the ground.

Abstract: A capacitor array structure which includes N capacitor units is provided. Each capacitor unit includes a first metal layer, a second metal layer, and a third metal layer to form an upper electrode and a lower electrode. The second metal layer is disposed between the first metal layer and the third metal layer, and includes a second patterned metal portion of the lower electrode and a first patterned metal portion of the upper electrode. disposed above. The second patterned metal portion of the lower electrode has an opening, and a side of the first patterned metal portion of the upper electrode is exposed in the opening, such that the side of the first patterned metal portion of the upper electrode is adjacent to the lower electrode of another capacitor unit.