Abstract: A method of fabricating a patterned polyimide film on a semiconductor wafer including spin coating the wafer with a polyimide precursor solution, baking the polyimide precursor solution in order to remove solvents from and to slightly cure the solution to form a polyimide film, and rinsing the polyimide film with deionized water immediately following the baking step prior to further processing. The rinsing in part serves to further remove solvents associated with the polyimide film. The process continues with photolithography techniques in which the wafer spin coated with a selected photoresist to form a photoresist film immediately following the rinsing step, and a baking of the photoresist film. Thereafter, the photoresist film is exposed to radiation through a photomask, and developed with a solution to form a pattern. The pattern is then etched into the polyimide film with the solution. The remaining portions of the photoresist are removed with a chemical stripper.

Abstract: A Hall transducer produces a signal Vsig. Threshold voltages V.sub.Pth and V.sub.Nth are generated at the beginning, t.sub.update, of each of a succession of update time intervals, of 64 pulses in Vsig, to be fixed percentages respectively of the peak to peak voltage in Vsig. A proximity-detector binary output voltage is high when Vsig exceeds threshold voltage V.sub.Pth and low when Vsig is below threshold voltage V.sub.Nth. Signals V.sub.Pold and V.sub.Nold, generated by first and second DACs, are equal to the first positive and negative peaks in Vsig after each time t.sub.update initiating the start of a successive interval. Signals V.sub.Pnew and V.sub.Nnew, simultaneously generated by third and fourth DACs, are equal to the greatest positive and negative peak voltages in Vsig during the interval ending at t.sub.update. Counters present their count to the first and second DACs that count pulses from a clock for tracking and holding +/- peaks in Vsig. After each time t.sub.

Abstract: A chopped Hall sensor includes a Hall-element switching circuit of the kind in which a Hall element has two pairs of diagonally opposite Hall contacts which are alternately connected to a pair of DC supply conductors and to a pair of Hall-stitching-circuit output conductors for alternately, during phase .phi.1 and n.phi.1 of a first clock signal, switching the Hall exciting current from flow in one to another direction through the Hall element. A linear analog double-differential Hall-voltage amplifier has an input connected to the output of the Hall switching-circuit. A sample-and-hold circuit is comprised of first and second elemental sample-and-hold circuits (ESHCs) with inputs connected respectively to the two Hall-voltage differential-amplifier outputs. The first and second ESHCs are respectively clocked, by second and third clock signals, to the sample Hall voltage signal only during phases .phi.2 and .phi.3 and to hold the sample signal during phases n.phi.2 and n.phi.3 respectively, where .phi.2 and .

Abstract: A low power magnetic-field detector, of the kind for detecting an ambient magnetic field that is greater than a predetermined field strength, is comprised of a Hail element, a transducer-voltage amplifier, and a zero-crossing comparator, all connected in tandem. A clock and switch are used to chop the energizing current to the Hall element. Alternatively, the amplifier and comparator are also chopped to further reduce power consumption. A clockable flip flop is synchronously enabled for an instant at the end of each period of energizing the Hall element. The comparator output signal is transferred to the flip flop Q output and held there during each period of not energizing the Hall element. A Positive-feedback hysteresis circuit adds a bias voltage to the amplified Hall voltage and is applied to the comparator input to effect comparator hysteresis with memory covering clock-period portions when the Hall element is not energized.

Abstract: This invention is a magnetic-field sensor assembly comprising a preformed housing shell having a first end which includes an opening, and a second end which includes a window and having a cylindrical shape with a flattened portion to produce a truncated circular cross-section, a sensor package including an integrated-circuit magnetic-field-sensor chip encapsulated in a protective body with first and second opposite and mutually parallel faces and a plurality of integral conductive leads, each lead having a proximal portion, a distal portion, and a central portion, the proximal portion of each of said plurality of leads extending from said body, the central portion of said plurality of leads extending away from the body and positioned substantially normal the faces of the body, said sensor-package body being positioned in said housing shell part way through said window with said one body face extending outwardly from said housing shell and with said lead distal portions extending from said housing shell throug

Abstract: A semiconductor integrated circuit has a P-type substrate and a plurality of PN-junction isolated islands of N-type, a first one of the islands may contain a power device which during certain periods of operation causes the first island to become forward biassed and to inject electrons into the substrate. Collection of these injected charges by a second island at one side of the injecting island is reduced by a separate protective bipolar transistor formed in a third N-type island. The third island is preferably interposed between the injecting island and the islands to be protected, but may be located anywhere with respect to the injecting transistor. The emitter of the protective transistor is electrically connected to an N-type portion of the first island. The collector of the protective transistor is connected to the P-type isolation-wall portion of the substrate located between the injecting transistor and the small islands to be protected.

Abstract: There is added to a conventional magnetic-field detector, which includes a magnetic-field-to-voltage transducer such as a Hall element connected to a Schmitt trigger circuit, a DC voltage monitor circuit to produce a high binary monitor signal only when the DC supply voltage is within a predetermined normal band, and a logic circuit having one input connected to the output of the monitor circuit and a second input connected to the output of the Schmitt trigger circuit. During periods when the binary-Schmitt-output voltage remains high, corresponding for example to a high ambient magnetic field, noise spikes on the DC line can cause an anomalous change in the binary-Schmitt-output voltage of a magnetic-field detector from a high level to a low level.

Abstract: In an integrated circuit in which a first PN-junction-isolated island may momentarily become forward biased with respect to the surrounding substrate and inject unwanted charge that is collected by second islands adjacent one side of a first island, the injected charge is drawn away from the second islands and to a gatherer-collector island located at another side of the first island. The first island, gatherer-collector island and intervening substrate therebetween serve respectively as the emitter, collector, and base of a protective transistor. This transistor becomes a highly efficient collector of injected charge when the protective-transistor collector is hard wired to ground and the protective-transistor base is hard-wire connected to the substrate portion between the injecting first island and adjacent second island.

Abstract: An FM stereo radio data-system receiver has a front end including an FM discriminator that produces a composite signal composed of an AM stereo signal, including a 19 KHz pilot, and an AM digital-data signal. A dual-bandwidth phase locked loop (PLL) locks onto the pilot and serves both, as the decoder of the stereo portion of the composite signal, and as a generator of a strong stable 38 KHz carrier for use in regenerating the bit rate clock signal and for decoding the data-symbol signal of the digital-data portion of the composite signal. Advantages include economy of circuitry, a simpler and less costly high pass filter, and greater reliability in the decoding of the data signal.

Abstract: A disc drive circuit includes a pair of DC busses across which are directly connected a disc actuator power amplifier and a three phase spindle motor power amplifier which may be comprised of three circuit branches, each branch having two NMOS transistors connected in series with the junction therebetween connected to one of three spindle motor terminals. A transistor switch is connected between a DC supply source and the DC busses for disconnecting the busses from the voltage source only when the supply voltage drops below a nominal operating voltage range. In one embodiment a full wave diode rectifier is also directly connected across the pair of busses and further connected to the three motor terminals, whereby when the switch is open the back e.m.f. of the free spinning spindle motor energizes the actuator amplifier enabling parking of the actuator heads. In another embodiment the drain to channel regions of the six NMOS transistors are adapted to assume the role of a full wave rectifier.

Abstract: A full-bridge driver, and especially an entirely integrated bridge driver, for driving DC motors in either direction is capable of automatically braking the motor when the motor direction is to be reversed. The bridge circuit is of "H" configuration and has four transistor switches connected in bridge configuration and has two bridge output terminals to which a motor may be connected. A differential window comparator has the input connected to the two bridge output terminals, producing a high level binary signal only when the voltage across the two output terminals is within a small voltage range centered at about zero volts. A pulse-width filter circuit having an input connected to the window comparator produces a high binary output signal only when the comparator-produced binary signal remains high for greater than a predetermined time.

Abstract: A bridge circuit, intended for use as a PWM driver of an inductive load, includes at least one source driver transistor connected in series totem-pole fashion with a sink driver transistor. A base resistor is connected from base to emitter of one of the driver transistors. This totem pole circuit is connected across a pair of DC supply conductors. A protective fly-back diode is connected across the one driver transistor. An auxiliary resistor is connected from the base of the auxiliary transistor to the emitter of the one driver transistor. When a fly-back diode across the one driver transistor conducts, the one driver transistor tends to conduct in the reverse direction and to store charge that in a subsequent period leads to shoot-through currents through the source and sink drivers.

Abstract: A full-wave bridge driver has four driver transistors. A motor is connected to the output terminals of the bridge. A fault detector latches off the four driver transistors when the bridge current jumps essentially instantaneously to exceed a predetermined safe-peak value due to a fault occurring in the bridge. A comparator has a predetermined current threshold, that is less than the predetermined safe-peak value of the fault detector, and is connected to a bridge-current sensing resistor for, when the bridge current exceeds the current threshold, producing a signal proportional to the difference between the bridge current and the current threshold. A pulse-width-modulator is connected to the comparator means output, and during periods such as at motor starting when the bridge current gradually exceeds the comparator threshold value, chops the signal at the bases of the four driver transistors, varying the chopped pulse widths to hold the motor current at essentially the threshold current value.

Abstract: The Hall sensor circuit includes a Hall element that is preferably followed by a Hall-voltage amplifier, and a pole end of a magnet is preferably fixed adjacent to the Hall element. The amplifier output is connected directly to one of a pair of differential inputs of a Schmitt trigger circuit and is also connected, via a single or a dual-polarity track and hold circuit, to the other of the differential Schmitt inputs. The dual-polarity track and hold circuit causes the voltage across a capacitor to track positive and negative Hall voltage slopes, and to hold the positive-going peaks and negative-going peaks of the Hall voltage presented to the fore-mentioned other Schmitt input so that when the difference voltage between the Hall voltage and the held voltage of the capacitor exceeds a positive or negative threshold of the Schmitt circuit, the Schmitt circuit output changes binary state indicating the approaching edge or the receding edge of a ferrous-gear tooth.

Abstract: A current source circuit includes at least three pairs of bipolar transistors of the same polarity type. The first transistors of each pair are connected in one series circuit string emitter to collector. The second transistors of each pair are connected in another circuit string. The first-pair second transistor is connected emitter to collector with the second-pair second transistor while the emitter of the second-pair second transistor is connected to the base of the third-pair second transistor which serves as the output transistor. The first transistors of the first and third pairs have their bases connected respectively with their collector. The bases of the two second-pair transistors are cross coupled with the collectors of the second-pair transistors.

Abstract: A temperature-compensated current source energizes a Hall element. The current source includes a voltage divider across the DC voltage supply busses and a differential amplifier arranged as a voltage follower which develops the output voltage across a reference resistor, creating a reference current which is amplified to generate a Hall energizing current. This results in a Hall element gain which is controllable over temperature. The temperature coefficient of the resistor can be chosen to compensate for the sensitivity temperature coefficient of a Hall element powered by a constant current source. Additionally, the temperature coefficient of the resistor may be chosen to compensate for the temperature coefficient of a magnet used to generate the magnetic field which the Hall element is intended to detect. The magnitude of the Hall current, and thus the Hall element gain, is directly proportional to the magnitude of the DC voltage supply.

Abstract: An electrical power distribution system of an industrial plant or a commercial building and having a capacity for delivering at least 500 KVA, includes a voltage step-down transformer connected between an AC source of electrical energy and a pair of power distribution line conductors across which there is connected a pulsed inductive load, such as a motor with a thyrister speed controller. The power factor of the system is corrected by a power factor correction capacitor connected directly across the system power distribution line conductors. Pulsed inductive loads tend to excite large harmonic currents in such systems having both a transformer and a power factor correction capacitor directly across the distribution line conductors. A filter, made up of a filter capacitor and a filter inductor tuned exactly to one harmonic, are connected in a series circuit branch that is connected directly across the system power distribution line conductors.

Abstract: A notch filter circuit includes first and second operational amplifiers, each having a capacitor connected from the amplifier output to the input. A third capacitor is connected between the second-amplifier input and the filter circuit input. A first switched-capacitor resistor is connected between the filter circuit input and the first-amplifier input. A second switched-capacitor resistor is connected between the first amplifier output and the second amplifier input. The second-amplifier output is connected to the filter circuit output.

Abstract: The lead-frame in an integrated circuit package, a standard package designated SOT-89, has a plurality of leads of which at least one is an extension of a die-attach pad. At least one ground wing is formed as an extension of a peripheral portion of the die-attach pad and extends upward to approximately the plane of the top of the die. The ground wing has an upstanding portion and a horizontal portion that are at an angle to each other so as to lock the distal end of the wing in the body of encapsulating resin. An integrated circuit die having at least one electrical connection which is grounded electrically via a terminal and wire bonded to the distal part of the ground wing. A contact surface near the distal end of wing is positioned approximately in the plane of the top of the die. This ground circuit can parallel and can be redundant to a ground circuit through the die via the conductive bond that attaches the bottom of the die to the die-attach pad.

Abstract: In a method for assembling a lead frame between two plate-mold cavity plates, a lead frame that includes a plurality of integrated circuit chips mounted spaced at intervals in a row thereon, is placed on a bottom one of the cavity plates which has a row of cavities spaced apart at the same intervals as the integrated circuit chips, each chip being positioned over a corresponding cavity. The bottom cavity plate is held about horizontal on the base plate of an assembly fixture. Two short guide pins extend upward from the cavity plate, the lead frame having two pilot holes directly above the guide pins. Accurate positioning of the lead frame will permit penetration of the pilot holes by the guide pins.