Abstract: A programmable PD servo compensator has the transfer function of the combination of a standard PD compensator in tandem with a second order low pass filter. The programmable PD servo compensator consists simply of a biquad filter having a single complex zero and a pair of conjugate complex poles. This servo compensator is comprised of two tandem connected operational amplifiers, each with a capacitor connected output to input across it. The tandem connection is effected by one switched-capacitor resistor between the output of the first amplifier to the input of the second. Another switched-capacitor resistor is connected between the PD compensator input and the input of the first amplifier. Yet another switched capacitor is connected between the PD compensator output and the input of the first amplifier.

Abstract: An electrical power controller includes an integrated circuit having a Hall element, a Hall voltage amplifier, a ramp signal generator, and a voltage comparator. The output of the ramp generator is connected to one input of the voltage comparator and the output of the Hall voltage amplifier is connected to the outer comparator input. During intervals when the amplified Hall voltage exceeds the ramp voltage, the output of the comparator changes from one binary state to the other such that a stream of pulses is generated at the output of the comparator. Thus as a magnetic field at the Hall element increases, the Hall voltage increases and the width of each pulse in the stream of pulses grows proportionally. Mechanical means is provided for manually moving and guiding the pole of a magnet along a path toward the integrated circuit. Constructions of such controllers adapted for use as lamp dimmers and DC motor speed controllers are described.

Abstract: Analog-signal integrators are described that have a transfer function containing a composite parameter that is the product of two parameters each of which is separately changeable, via application of digital programming signals. In a continuous analog-signal integrator the integrating capacitor is a programmable capacitor array, preceded in the feed back branch with a programmable voltage divider. In a discrete-time analog-signal integrator the integrating resistor is a switched-capacitor resistor including a programmable capacitor array that is preceded in the input circuit branch by a programmable voltage divider.

Abstract: A digitally programmable integrated-circuit analog-signal servo co-processor has digital programming contact pads to which an external microprocessor may be connected, has analog-signal input pads and analog-signal output pads, and includes a plurality of programmable analog-signal-manipulating circuits (ASMC's). Each of the ASMC's has input and output terminals connected to an input programmable-switch matrix so that one or a combination of the ASMC blocks may be connected between the analog-signal input and output contact pads of the integrated circuit. Certain ASMC blocks have microprocessor programmable transfer functions, e.g. ASMC integrator, notch filter, low pass filter, PD compensator and voltage divider. Key ones of those ASMC blocks are discrete-time circuits including switched-capacitor resistors and have transfer functions wherein the parameters are ratios of capacitances and the switching rate frequency to provide accurate and stable performance.

Abstract: An integrated circuit chip includes a MOS driver transistor and a relatively small MOS current-monitor transistor having their sources connected to a circuit ground point and their gates connected together to a control-voltage conductor. Current through the monitor transistor flows to a DC voltage supply conductor through a field effect transistor. A differential amplifier has one input connected to the drain of the driver transistor and the other input connected to the drain of the monitor transistor. The output of the differential amplifier is connected to the gate of the field effect transistor to force the drain voltage of the monitor transistor to be equal to the drain voltage of the driver transistor. The current flowing through the small monitor transistor has a constant proportionality with the load current even as the load current approaches zero.

Abstract: A magnetic-field monitor includes a Hall sensor of the kind having a voltage reference terminal and a signal output terminal for being energized by applying a DC voltage across the output terminal and the reference terminal, and generates through the output terminal a low value current when the ambient magnetic field strength is low and a high output current when the magnetic field is high. The Hall sensor is connected via a pair of conductors to a Hall-sensor decoder circuit that is energized by a DC voltage source and in turn energizes the sensor via the pair of conductors. The decoder includes a current mirror circuit that mirrors the Hall-sensor current into a voltage divider. Three voltage comparators having different threshold voltages are connected at three points in the voltage divider.

Abstract: An amplifier has a first stage employing a pair of differentially connected NMOS amplifier transistors, a second stage composed of a bipolar current mirror circuit and two charge pumps. Each charge pump may be a switching voltage multiplier circuit without the conventional output capacitor. The outputs of the two charge pumps are connected, respectively, to the collector of the current-mirror output transistor and to the commonly connected sources of the NMOS amplifier transistors. Each charge pump serves as both a pulse-voltage energizing source and a load to the amplifier. The amplifier is incorporated with a high-current NMOS transistor in an integrated circuit, wherein one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected.

Abstract: A stereo decoder for use in a stereo FM radio receiver includes a phase-locked loop; for detecting the 19 KHz pilot signal in the FM composite signal; for generating the 38 KHz subcarrier for use as a reference signal to a double balanced gating circuit that combines he L-R and L+R components of the stereo composite signal to produce the left audio and right audio signals separately; and for providing a 19 KHz reference signal for use in the pilot detector and pilot indicator circuit. The phase-locked loop includes a mixer to which a 19 KHz reference and the composite signals are applied, a low pass filter switchable from a first bandpass of about 300 Hz to a second bandpass of about 10 Hz connected to the output of the mixer a voltage controlled oscillator connected to the output of the filter that has a natural operating frequency of 38 KHz and a divide-by-two circuit connecting the oscillator to an input of the mixer.

Abstract: A lead frame and die sub-assembly is first manufactured by a conventional method including bonding a die to the die attach pad of a lead frame and connecting wires between the die and the lead frame fingers. The sub-assembly is stacked first adjacent a dielectric plastic sheet that is in turn stacked against a metal heat spreader block. The dielectric sheet has a centrally located hole registered with the die attach pad. A dollop of an uncured resin is dispensed in the gap between the die attach pad and block. This assembly is compressed between two hot platens whereby the lead fingers, dielectric sheet and the block are bonded together and the resin dollop is flattened to a controlled thickness, namely the thickness of the dielectric sheet. The thickness of the dielectric sheet controls the flattened thickness of the cured resin dollop.

Abstract: A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, selectively etching a hole in the glass layer at an emitter-designated place over the preliminary base region, depositing N-type impurities through the hole into the silicon surface to become the emitter, implanting P-type impurities, of a kind that diffuse faster than the N-type impurities, through the hole into the epitaxial layer and heating to at least anneal the substrate. The hole is then filled to provide electrical contact to the emitter.

Abstract: A bipolar chopping driver circuit has a pair of NPN totem-pole connected driver transistors with a fly-back diode connected across the NPN source transistor and a biasing resistor connected between base and emitter of the source transistor. A fullwave bridge driver may be comprised of two such totem pole circuits with the inductive load connected between them at the junctions between NPN source and sink transistors. A clamp circuit is provided in both cases, for preventing the voltage swings at the bases of the source transistors from exceeding the DC supply voltage that is connected to the collectors of the source transistors, thereby permitting operation at high chopping frequencies without excessive delay in switching load current and excessive power losses.

Abstract: An integrated circuit voltage chop circuit for regulating the current in an inductive load is of the type having a fixed off time. A current-sensing comparator produces a reset signal when the current through the driver exceeds a predetermined peak amplitude. A load driver transistor is turned on and off according to the state of a bistable memory elememt, e.g. a flip flop. An external capacitor and external series resistor are connected to the integrated circuit and they determine the driver off time. A voltage comparator having hysteresis produces a high output logic level when the capacitor charges to a predetermined voltage which sets the flip flop and begins to slowly discharge the capacitor. When the capacitor discharges to a lower predetermined voltage, the voltage comparator output goes to a low logic level turning on a shorting transistor that quickly discharges the capacitor completely.

Abstract: A multistation computer system includes a host computer and a plurality of workstations coupled to the host computer by a communications bus. The host computer is coupled to the communications bus by a host controller and each workstation is coupled to the communications bus by a workstation controller. When the host computer performs a data transaction with a workstation, the host controller monitors the bus signals on the host computer and determines which workstation is being addressed. The host's bus signals are then encoded and sent to the appropriate workstation in a data packet transmitted over the communications bus. In the preferred embodiment the encoded bus signals are transmitted over an optical fiber bus which is daisy chained to all the workstation in the computer system and then back to the host computer. At the workstation the encoded bus signals are decoded and then asserted on the workstation's bus.

Abstract: A ferrous article proximity sensor package includes a dual Hall element IC chip mounted at the end of a magnet. The axis of the chip, defined as being orthogonal to the chip face and equidistant the two Hall elements, is coaxial with the outer wells of the package but spaced away from the axis of the magnet. That exact position is such that the resulting difference in magnetic field strength at the two Hall elements is just enough to compensate for all the other factors that lead to an unwanted offset voltage in the sensor output. This package is made of two mating parts, one containing the magnet being eccentric with respect to the chip axis and the other containing the chip just above one magnet pole end. To achieve the abovedescribed desired offset condition in manufacturing, the one package part is simply rotated with the magnet relative to and within the other package part until the desired condition is met, and the two parts fastened together in that position.

Abstract: A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from 950.degree. C. to 1100.degree. C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping.

Abstract: An FM stereo decoding and separating circuit has an (AM) demodulator multiplier to which is connected the FM stereo composite signal and a signal of dominant frequency equal to and in phase (0.degree.) with respect to the pilot signal for retrieving the L-R signal from the composite signal. This demodulator also has a blend control circuit for diminishing the magnitude of the L-R signal as a function of a blend control voltage that may be applied to the input of the blend control circuit. The decoding circuit also includes a special multiplier to which is connected the FM stereo composite signal and a signal of dominant frequency equal to that of the 38 KHz subcarrier but shifted 90.degree.

Abstract: A uniformly thick dielectric polyimide coating is provided on the back face of an integrated circuit and the die is mounted to a copper lead frame finger by interposing an epoxy resin bonding agent between the uniformly thick polyimide coating and the copper support finger. The die coating is provided before separating die from the precursive water. Liquid polyimide is poured onto the back side of the water which is spun, in a manner similar to that usually used for obtaining uniformly thick photoresist films. After curing the polyimide, the die are cut from the wafer by sawing.