Patents Assigned to Alpha and Omega Semiconductor Incorporated
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Patent number: 10522666Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.Type: GrantFiled: March 9, 2018Date of Patent: December 31, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
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Patent number: 10446679Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.Type: GrantFiled: January 30, 2019Date of Patent: October 15, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
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Patent number: 10446545Abstract: A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.Type: GrantFiled: June 30, 2016Date of Patent: October 15, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Sik Lui
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Patent number: 10439058Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.Type: GrantFiled: June 27, 2018Date of Patent: October 8, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Tinggang Zhu
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Patent number: 10424654Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.Type: GrantFiled: June 27, 2018Date of Patent: September 24, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang, Jowei Dun, Hongyong Xue, Yiming Gu
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Patent number: 10418899Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.Type: GrantFiled: April 14, 2014Date of Patent: September 17, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sik K. Lui, Daniel S. Ng, Xiaobin Wang
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Patent number: 10411104Abstract: Forming a semiconductor device on a semiconductor substrate having a substrate top surface includes: forming a gate trench extending from the substrate top surface into the semiconductor substrate; forming a gate electrode in the gate trench; forming a curved sidewall portion along at least a portion of a sidewall of the gate trench; forming a body region adjacent to the gate trench; forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion; forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.Type: GrantFiled: December 19, 2016Date of Patent: September 10, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventor: John Chen
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Patent number: 10411692Abstract: A controller for driving a power switch incorporates a protection circuit to protect the power switch from fault conditions, such as over-voltage conditions or power surge events. The protection circuit includes a fault detection circuit and a protection gate drive circuit. The fault detection circuit is configured to monitor the voltage across the power switch and to generate a fault detection indicator signal and the protection gate drive circuit is configured to generate a gate drive signal to turn on the power switch in response to a detected fault condition. In particular, the protection gate drive circuit generates a gate drive signal that has a slow assertion transition and is clamped at a given gate voltage value. In this manner, the protection circuit implements active clamping of the gate terminal of the power switch and safe handling of the power switch during over-voltage events.Type: GrantFiled: November 23, 2016Date of Patent: September 10, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Bum-Seok Suh, Wonjin Cho, Son Tran
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Patent number: 10404169Abstract: The invention proposes a system and method for extending the maximum duty cycle of a step-down switching converter to nearly 100% while maintaining a constant switching frequency. The system includes a voltage mode or current mode step-down converter driven by a leading edge blanking (LEB) signal, which operates at the desired switching frequency. More particularly, the LEB signal is connected to a slope generator and/or a current sense network. In each switching cycle, the LEB signal forces the slope signal and/or current sense signal to reset, thereby achieving a constant switching frequency. Corresponding methods for how to extend the maximum duty cycle of a step-down switching converter while maintaining a constant frequency are also disclosed.Type: GrantFiled: September 24, 2015Date of Patent: September 3, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Youngbok Kim
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Patent number: 10396158Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.Type: GrantFiled: July 26, 2018Date of Patent: August 27, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 10388781Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.Type: GrantFiled: May 20, 2016Date of Patent: August 20, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Madhur Bobde, Sik Lui, Ji Pan
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Patent number: 10354990Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.Type: GrantFiled: September 30, 2017Date of Patent: July 16, 2019Assignee: Alpha and Omega Semiconductor incorporatedInventor: Madhur Bobde
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Patent number: 10333006Abstract: A method for forming a nitride-based Schottky diode includes forming a nitride-based epitaxial layer on a front side of a nitride-based semiconductor body; forming a first dielectric layer on the nitride-based epitaxial layer; etching the first dielectric layer and the nitride-based epitaxial layer to the nitride-based semiconductor body to define an opening for an anode electrode of the nitride-based Schottky diode and to form an array of islands of the nitride-based epitaxial layer in the opening, the first dielectric layer having an end that is recessed from an end of the nitride-based epitaxial layer near the opening. In another embodiment, the first dielectric layer and the nitride-based epitaxial layer have a slant profile at a side facing the opening for the anode electrode.Type: GrantFiled: June 26, 2018Date of Patent: June 25, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
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Patent number: 10325908Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.Type: GrantFiled: April 26, 2017Date of Patent: June 18, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Sik Lui, Madhur Bobde, Ji Pan
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Patent number: 10319848Abstract: A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.Type: GrantFiled: June 25, 2018Date of Patent: June 11, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Hideaki Tsuchiko
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Patent number: 10297594Abstract: A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.Type: GrantFiled: August 6, 2015Date of Patent: May 21, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Jongoh Kim, Hong Chang
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Patent number: 10276387Abstract: A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.Type: GrantFiled: February 2, 2017Date of Patent: April 30, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Karthik Padmanabhan, Madhur Bobde, Lingpeng Guan, Lei Zhang, Hamza Yilmaz
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Patent number: 10256236Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.Type: GrantFiled: August 2, 2018Date of Patent: April 9, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Ji Pan, Sik Lui
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Patent number: 10250152Abstract: A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding current to turn off the synchronous rectifier and to start the next switching cycle. At this point, the voltage across the primary switch has been discharged and the primary switch can be turned on with zero drain-to-source voltage. In other embodiments, zero voltage switching for the off-transition of the primary switch is realized by coupling a capacitor across the primary switch or by coupling a capacitor across the primary winding, or both.Type: GrantFiled: May 4, 2018Date of Patent: April 2, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Kuang Ming Chang, Lin Chen, Qihong Huang
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Patent number: 10243072Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.Type: GrantFiled: May 4, 2018Date of Patent: March 26, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz