Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Abstract: An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.

Abstract: A transmitter circuit applicable to a digital isolator is provided, adapted to receive a data input signal and coupled to an isolation barrier, developing a receiver input signal to a receiver circuit for generating a data output signal. The transmitter circuit generates a transmitter output signal in response to a rising edge and falling edge of the data input signal, and includes a rising and falling converter for outputting a converted data input signal according to the rising edge and falling edge of the data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, and an AND gate receiving the converted data input signal and the carrier signal, and outputting the transmitter output signal. Since a number of pulses of the carrier signal is limited and definite, the present invention achieves to reduce power consumption and electromagnetic interferences effectively.

Abstract: A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal. The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.

Abstract: A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.

Abstract: A digital isolator module with pulse carrier modulation is provided, comprising an isolation barrier, operable to develop an isolated output signal in response to an input signal, a transmitter circuit adapted to receive a data input signal and coupled to the isolation barrier, and a receiver circuit coupled to the isolation barrier to receive the isolated output signal and generate a data output signal. The transmitter circuit is adapted to be operable to generate a transmitter output signal in response to the data input signal, and the transmitter output signal comprises different number of pulse carrier respectively responsive to a rising edge and a falling edge of the data input signal. By employing the proposed pulse carrier modulation of the present invention, it has been verified to reduce channel numbers, IC power consumption and electromagnetic interferences. In addition, jitter disturbances can be avoided and solved effectively.

Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Abstract: A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.

Abstract: A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.

Abstract: A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: A bidirectional electrostatic discharge protection device and a method for fabricating the same is disclosed. The protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, a heavily-doped area, and a lightly-doped area. The substrate, the heavily-doped area, and the lightly-doped area have a first conductivity type and the epitaxial layers have a second conductivity type. The first semiconductor epitaxial layer and the second semiconductor epitaxial layer are sequentially formed on the substrate, and the heavily-doped area and the lightly-doped area are formed in the second semiconductor epitaxial layer.

Abstract: A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.

Abstract: A receiver circuit with input common mode voltage sensing is provided. The receiver circuit is applied to a controller area network and comprises a resistor assembly, connected with a high end and a low end of the controller area network, a common mode voltage sensor and a receiving amplifier. The resistor assembly bucks voltage, respectively generating the high end and low end voltage divisions at first and second nodes and outputting the voltage divisions to the receiving amplifier to generate a resultant signal to an output end of the controller area network. The common mode voltage sensor is connected between the resistor assembly and the receiving amplifier, and able to sense the common mode voltage on bus and control the voltage on center tap of the resistor assembly so the receiver circuit for controller area network can receive the differential signal with a much wider input common mode range.

Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Abstract: An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.

Abstract: A multi-channel transient voltage suppressor with ultra-low capacitance is provided, which comprises a plurality of diode strings coupled between an ESD bus line and ground, having each diode string coupled to an I/O pin; a power clamp circuit coupled to the ESD bus line; and a first diode having an anode coupled to the power clamp circuit and a cathode coupled to ground. A second diode may be alternatively disposed between the first diode and the diode strings, having an anode coupled to the ground and a cathode coupled to a common anode of the diode strings. By employing the proposed present invention, it is advantageous of reaching an ultra-low capacitance and meanwhile still maintaining a lower layout area of the circuit structure.

Abstract: A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.