Abstract: A digital isolator module having additional delay path is provided, comprising a transmitter circuit receiving a data input signal and generating a first and second transmitter output signal. The second transmitter output signal is a delay signal of the first transmitter output signal. An isolation barrier is then configured, accordingly developing a first and second isolated output signal. And a receiver circuit accordingly generates a data output signal in response to the first and second isolated output signals. By employing a delay circuit in the disclosed transmitter circuit for delaying the first transmitter output signal and generating the second transmitter output signal, receiving signals at the receiver input terminal can be enhanced, robustness of data transmission is greatly improved and common mode voltage instability is suppressed.

Abstract: A transmitter circuit is provided having an additional delay path. A first transmitter output signal is generated according to a rising edge and falling edge of its data input signal. A second transmitter output signal is generated by delaying the first transmitter output signal. The disclosed transmitter circuit includes a rising and falling converter for outputting a converted data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, an AND gate receiving the converted data input signal and the carrier signal, and outputting the first transmitter output signal, and a delay circuit receiving the first transmitter output signal and outputting the second transmitter output signal. Robustness and common mode voltage stability can be enhanced. Due to a definite and limited number of pulses of the carrier signal, the invention also achieves to reduce power consumption and electromagnetic interferences effectively.

Abstract: An electrostatic discharge protection device includes a diode, a voltage clamping component, an electronic component, a first pin, and a second pin. The diode includes a first doped area of a first conductivity type and a second doped area of a second conductivity type opposite to the first conductivity type. The voltage clamping component is electrically connected to the first doped area. The electronic component includes a first region of the first conductivity type, a second region of the second conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type. The first region is electrically connected to the second doped area. The second region is electrically connected to the first doped area and the voltage clamping component. The fourth region is electrically connected to the voltage clamping component.

Abstract: A transient voltage suppressor is provided, including a semiconductor substrate and a doped well of first conductivity type, an epitaxial layer of second conductivity type, first and second heavily doped regions of second conductivity type, and a third heavily doped region of first conductivity type in the doped well. The first heavily doped region is connected to a fourth heavily doped region of second conductivity type, and the fourth heavily doped region and a fifth heavily doped region of first conductivity type are disposed in the epitaxial layer. A sixth heavily doped region of second conductivity type is disposed in the epitaxial layer and connected in common with the third heavily doped region in the doped well. The fifth and second heavily doped regions are connected to I/O and ground, respectively. When applying a positive surged mode, the disclosed transient voltage suppressor is characterized by providing multiple discharging paths.

Abstract: A transmitter circuit with ringing suppression applicable to a controller area network bus is provided, which includes a CAN bus driver stage receiving a transmit data signal and generating a CAN high voltage signal and a CAN low voltage signal, a first operational transconductance amplifier electrically connected with the CAN bus driver stage for receiving the CAN high voltage signal, and a second operational transconductance amplifier electrically connected with the CAN bus driver stage for receiving the CAN low voltage signal. A common mode voltage of a dominant state as well as a control signal are applied such that when the control signal is logically high, the first and second operational transconductance amplifiers actively pulls the CAN high voltage signal and the CAN low voltage signal to be equal to the common mode voltage of the dominant state so as to suppress ringing phenomenon occurring in the CAN bus.

Abstract: A digital isolator circuit with serially connected isolation capacitors is provided, comprising a first integrated circuit region and a second integrated circuit region. A first transceiver and a plurality of serially connected high-voltage isolation capacitors are configured in the first integrated circuit region. A second transceiver and a plurality of serially connected high-voltage isolation capacitors are configured in the second integrated circuit region. A metal wire bonding is connected between the high-voltage isolation capacitors in the first and second integrated circuit region, but not in contact with the isolation capacitors connected to the first and second transceivers. Since the proposed digital isolator circuit is characterized by having serially connected isolation capacitors, damages to the dielectric layer caused by the metal wire bonding can be suppressed, enhancing the entire yield, ensuring withstanding voltages and thus having higher tolerance to the wiring encapsulation environment.

Abstract: A transient voltage suppression device includes at least one N-type lightly-doped structure, a first P-type well, a second P-type well, a first N-type heavily-doped area, and a second N-type heavily-doped area. The first P-type well and the second P-type well are formed in the N-type lightly-doped structure. The first N-type heavily-doped area and the second N-type heavily-doped area are respectively formed in the first P-type well and the second P-type well. The doping concentration of the first P-type well is higher than that of the second P-type well. The first P-type well and the second P-type well can be replaced with P-type lightly-doped wells respectively having P-type heavily-doped areas under the N-type heavily-doped areas.

Abstract: A bipolar junction transistor is provided, including a semiconductor substrate and a doped layer of a first conductivity type, a doped well region of a second conductivity type formed in the doped layer, a first, second heavily doped region of the second conductivity type, and a third, fourth and fifth heavily doped region of the first conductivity type in the doped well region. The fifth heavily doped region is coupled with a first pin. The third and fourth heavily doped regions are coupled with a second pin. A sixth and seventh heavily doped region of the first conductivity type are disposed in the doped layer. The sixth and first heavily doped regions are connected in common. The seventh and second heavily doped regions are connected in common. When applying either a positive or negative surged mode, the bipolar junction transistor is formed, having both lateral and vertical conducting paths.

Abstract: An electrostatic discharge protection device includes a clamping bipolar junction transistor and at least one electrostatic discharge circuit coupled between a first-voltage rail and a second-voltage rail. The electrostatic discharge circuit includes a silicon-controlled rectifier and a diode. The anode and the cathode of the silicon-controlled rectifier are respectively coupled to an I/O port and the first-voltage rail. The cathode of the diode is coupled to the anode of the silicon-controlled rectifier and the I/O port. The anode of the diode is coupled to the second-voltage rail. The absolute value of the reverse breakdown voltage of the diode is greater than the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier, which is greater than the absolute value of the trigger voltage of the clamping bipolar junction transistor.

Abstract: A transient voltage suppression device includes at least one N-type lightly-doped structure, a first P-type well, a second P-type well, a first N-type heavily-doped area, and a second N-type heavily-doped area. The first P-type well and the second P-type well are formed in the N-type lightly-doped structure. The first N-type heavily-doped area and the second N-type heavily-doped area are respectively formed in the first P-type well and the second P-type well. The doping concentration of the first P-type well is higher than that of the second P-type well. The first P-type well and the second P-type well can be replaced with P-type lightly-doped wells respectively having P-type heavily-doped areas under the N-type heavily-doped areas.

Abstract: A transient voltage suppressor with adjustable trigger and holding voltages is provided, including a heavily doped substrate of a first conductivity type connected to a first node, a lightly doped epitaxial layer of a second conductivity type on the substrate, a first and third well region of the first conductivity type, a second well region of the second conductivity type, a first and third heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type. The heavily doped regions are commonly electrically connected to a second node, and individually disposed in the well regions. Trenches are disposed opposite in the substrate for electrical isolation. A floating base bipolar junction transistor and silicon controlled rectifier can be respectively formed under a positive and negative surged mode. Accordingly, the invention is advantageous of superior electrical performances, high layout flexibility and low area consumption.

Abstract: A bipolar junction transistor with adjustable gain is provided, including a semiconductor substrate and doped layer of a first conductivity type, a doped well region of a second conductivity type and a plurality of heavily doped regions. At least one detection circuit is provided with an input voltage and operable to generate an output voltage for a conducting layer to receive, such that current paths generated in the transistor can be determined when the input voltage varies under different operating conditions, including a normal operating mode, a positive and a negative surged operating mode. When a transient event takes place, the bipolar junction transistor is characterized by having a higher gain than it is operating in the normal mode. The proposed invention achieves in integrating the unidirectional and bidirectional electrical characteristics in the disclosed bipolar junction transistor structure by employing the detection circuit such that adjustable gain is obtained.

Abstract: An electrostatic discharge protection device includes a P-type substrate, an N-type well, a first P-type heavily-doped area, an N-type doped area, and a first N-type heavily-doped area. The N-type well is formed in the P-type substrate. The first P-type heavily-doped area is formed in the N-type well. The N-type doped area and the first N-type heavily-doped area are formed in the P-type substrate. The N-type doped area is coupled to the N-type well through an external conductive wire decoupled to the first P-type heavily-doped area. Alternatively, the P-type substrate and the N-type well are respectively replaced with an N-type substrate and a P-type well.

Abstract: A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

Abstract: A ringing suppression circuit applicable to a transmitter module in a controller area network is provided, which includes a CANH driver circuit, a CANL driver circuit, a first operable circuit transmitting a CAN high signal, a second operable circuit transmitting a CAN low signal, and a termination component connected between the first operable circuit and the second operable circuit. By sequentially turning on a first, second, and third transistor of the CANH driver circuit and sequentially turning on a fourth, fifth, and sixth transistor of the CANL driver circuit, conventional ringing phenomenon is effectively suppressed. A plurality of transistors may also be configured for implementing the CANH driver circuit or the CANL driver circuit for further reducing a glitch. The transmitter module employing the proposed ringing suppression circuit is able to pull the bus to a recessive state and meanwhile suppress the ringing and improve the maximum data rate.

Abstract: A bipolar junction transistor is provided, including a semiconductor substrate and a doped layer of a first conductivity type, a doped well region of a second conductivity type formed in the doped layer, a first, second heavily doped region of the second conductivity type, and a third, fourth and fifth heavily doped region of the first conductivity type in the doped well region. The fifth heavily doped region is coupled with a first pin. The third and fourth heavily doped regions are coupled with a second pin. A sixth and seventh heavily doped region of the first conductivity type are disposed in the doped layer. The sixth and first heavily doped regions are connected in common. The seventh and second heavily doped regions are connected in common. When applying either a positive or negative surged mode, the bipolar junction transistor is formed, having both lateral and vertical conducting paths.

Abstract: A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

Abstract: A bidirectional electrostatic discharge protection device includes at least one bipolar junction transistor and at least one silicon-controlled rectifier. The silicon-controlled rectifier is coupled to the bipolar junction transistor in series. The absolute value of the breakdown voltage of the bipolar junction transistor is lower than that of the silicon-controlled rectifier and the absolute value of the holding voltage of the bipolar junction transistor is higher than that of the silicon-controlled rectifier when an electrostatic discharge voltage is applied to the bipolar junction transistor and the silicon-controlled rectifier.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Abstract: A transient voltage suppression device includes at least one N-type lightly-doped structure, a first P-type well, a second P-type well, a first N-type heavily-doped area, and a second N-type heavily-doped area. The first P-type well and the second P-type well are formed in the N-type lightly-doped structure. The first N-type heavily-doped area and the second N-type heavily-doped area are respectively formed in the first P-type well and the second P-type well. The doping concentration of the first P-type well is higher than that of the second P-type well. The first P-type well and the second P-type well can be replaced with P-type lightly-doped wells respectively having P-type heavily-doped areas under the N-type heavily-doped areas.