Abstract: An apparatus comprising an interface and a processing circuit. The interface may be configured to receive (a) a video signal based on a targeted view in a vehicle and (b) one or more status signals from one or more sensors of the vehicle. The processing circuit may be configured to (A) analyze the video signal received from the interface and (B) detect a type of obstruction of a window of the vehicle visible in the video signal in response to (i) a classification of information in the video signal and (ii) one or more of the status signals. The processing circuit may (a) determine a confidence level for the type of obstruction, (b) activate one or more corrective measures when the confidence level is above a pre-defined threshold and (c) adjust the confidence level based on a response of the obstruction to the corrective measures.

Abstract: An apparatus includes a memory and a circuit. The memory may be configured to store an input image having a plurality of color channels. The circuit may be configured to (i) calculate a plurality of average values of each of the color channels in a plurality of windows around each of a plurality of pixel locations in the input image, (ii) calculate a plurality of feature values based on the average values using a feature extraction process and (iii) generate a plurality of likelihood values of a specific color at each of the pixel locations using the feature values in a color classification process.

Abstract: An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of chained pipelines. The circuit may be configured to (i) increment each of a plurality of counters associated with a data unit in a buffer in response to a request from a first pipeline of the chained pipelines to increment one of the counters. The first pipeline may generate the data unit in the buffer. A plurality of second pipelines of the chained pipelines may access the data in the buffer in response to the counters being incremented. The circuit may be further configured to (ii) receive a plurality of wake instructions from the counters and (iii) send another wake instruction to the first pipeline in response to reception of all of the wake instructions.

Abstract: An apparatus including a memory and a circuit. The memory may be configured to store a multidimensional array of data values. The circuit may be configured to (i) fetch a plurality of data vectors from the memory, where each of the data vectors comprises a plurality of the data values, (ii) calculate a plurality of modification values based on the data values, (iii) calculate a first value of a first window based on the data values, and (iv) calculate a second value of a second window by adding to the first value of the first window a next one of the modification values and subtracting from the first value of the first window a previous one of the modification values. The second window generally overlaps the first window in the multidimensional array along a particular axis.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) receive (i) a plurality of first samples selected from a first picture of a sequence of pictures, (ii) a plurality of smooth first samples corresponding to the plurality of first samples, (iii) a plurality of second samples selected from a second picture of the sequence of pictures, and (iv) a plurality of smooth second samples corresponding to the plurality of second samples, and (b) generate a plurality of adjusted first samples by combining the smooth first samples, the first samples, and the smooth second samples. The second circuit may be configured to generate a plurality of values based on the plurality of adjusted first samples and at least one of the plurality of first samples and the plurality of second samples. The first samples and the second samples generally have different levels of a lighting condition.

Abstract: An apparatus comprising a sensor, an interface and a processor. The sensor may be configured to generate a video signal based on a targeted view of a driver. The interface may be configured to receive status information about one or more components of a vehicle. The processor may be configured to generate a control signal in response to a determined field of view of the driver. The control signal may be used to adjust one or more mirrors of the vehicle. The field of view may be determined based on (i) the video signal and (ii) the status information.

Abstract: An apparatus includes a plurality of hardware engines and a scheduler circuit. The hardware engines may be configured to process a plurality of vectors using a plurality of operators. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more of the operators, (ii) determine a readiness of each of the operators and (iii) schedule the one or more operators in at least one of the hardware engines based on the readiness. The scheduler circuit may be implemented solely in hardware.

Abstract: An apparatus includes a processor circuit and a correction circuit. The processor circuit may be configured to receive a sequence of pictures. The correction circuit may be configured to (i) generate a motion score based upon target samples from a target picture and reference samples from one or more reference pictures of the sequence of pictures, (ii) generate a first weight value based upon the motion score and a first weight limit value, and (iii) generate a plurality of blended picture samples by combining the target samples and the reference samples based upon the first weight value.

Abstract: An apparatus comprising a plurality of image sensors configured to capture an image and a processor. The processor may comprise a buffer. The processor may be configured to (i) receive data from the image in a sequential order, (ii) perform cost calculations on the data, (iii) store the data in the buffer in a direction, (iv) when data corresponding to an end of a line of pixels of the image is stored, perform a second cost calculation on the stored data corresponding to the line and (v) reverse the direction of storing the data in the buffer. An order for the second cost calculations on the line of the data may be last in, first out. The data may be stored while the second cost calculations are performed. Data may not be removed from the buffer until the second cost calculation has been performed on the data.

Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.

Abstract: A method for temporal filtering based on motion detection between non-adjacent pictures. The method may compute a motion score by motion detection between a target area in a target picture and a first area in a non-adjacent one of a plurality of reference pictures; and temporal filter the target area with a second area in an adjacent one of the reference pictures based on the motion score to generate a filtered area in a filtered picture. At least one of (i) the motion score and (ii) the generation of the filtered area may be controlled by one or more gain settings in a circuit.

Abstract: An apparatus includes a plurality of hardware engines and a scheduler circuit. The hardware engines may be configured to process a plurality of vectors using a plurality of operators. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more of the operators, (ii) track a plurality of unscheduled operators that have not been allocated to the hardware engines, (iii) track a plurality of statuses of the hardware engines and (iv) allocate at least one of the unscheduled operators to at least one of the hardware engines based on the statuses. The at least one unscheduled operator may be processed in the at least one hardware engine. The scheduler circuit may be implemented solely in hardware.

Abstract: An apparatus comprises a memory, one or more hardware engines, and a processor. The memory may be configured to store a feature map pyramid comprising an original feature map and a plurality of scaled feature maps. The one or more hardware engines may be configured to perform pooling operations utilizing power of two down sampling. The processor may be configured to generate the feature map pyramid from the original feature map using said one or more hardware engines.

Abstract: An apparatus includes a processor circuit and an ID recycle circuit. The processor circuit may be configured to generate a component table while performing connected-component labeling on a digital image. The ID recycle circuit is generally in communication with the processor circuit. The ID recycle circuit may be configured to minimize a number of entries in the component table generated by the processor circuit.

Abstract: An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.

Abstract: An apparatus includes a sensor and a processor. The sensor may be configured to generate a video signal based on a targeted view from a vehicle. The processor may be configured to perform video analysis on video frames of the video signal to detect an object, perform a classification of the object, provide a confidence level of the classification and generate a control signal in response to the classification of the object. The control signal may be used to reshape a beam of one or more headlights of the vehicle. The reshaping of the beams of the headlights may be determined based on a location of the object in the video frames and the confidence level of the classification. The confidence level of the classification of the object may be adjusted in response to a second classification of a second object detected in the video frame.

Abstract: An apparatus includes a plurality of cameras and a circuit. The cameras may be mounted on a vehicle and configured to generate a plurality of initial video signals of a scene outside of the vehicle. A plurality of fields of view of adjoining ones of the cameras may spatially overlap each other. The circuit may be configured to (i) store calibration values of the cameras generated during a calibration process, (ii) modify at least one of the initial video signals by applying the calibration values and (iii) generate a final video signal suitable to display to a user of the vehicle by stitching together the initial video signals. The calibration values may be used by the circuit to generate approximately continuous brightness within the scene in the final video signal.

Abstract: An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of chained pipelines. The circuit may be configured to (i) increment each of a plurality of counters associated with a data unit in a buffer in response to a request from a first pipeline of the chained pipelines to increment one of the counters. The first pipeline may generate the data unit in the buffer. A plurality of second pipelines of the chained pipelines may access the data in the buffer in response to the counters being incremented. The circuit may be further configured to (ii) receive a plurality of wake instructions from the counters and (iii) send another wake instruction to the first pipeline in response to reception of all of the wake instructions.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: An apparatus includes a memory and a circuit. The memory may be configured to store data. The circuit generally includes a local buffer. The circuit may be configured to (i) fetch all or a portion of a first array of values from the memory to the local buffer, (ii) fetch all or a portion of a second array of values from the memory to the local buffer, (iii) calculate an intermediate array of values by multiplying a converted version of the first array by a converted version of the second array, and (iv) calculate an output array comprising a plurality of output values based on values of the intermediate array and a predefined dimensional reduction.