Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus comprising a suction cup and a camera. The suction cup has an aperture. The camera is attached to the suction cup such that the camera can capture images through the aperture of the suction cup and a surface to which the suction cup is attached while the suction cup is attached to the surface.

Abstract: A method for synchronizing a first circuit to an electro-optical sensor is disclosed. The method generally includes steps (A) to (D). Step (A) may generate with the first circuit a configuration signal that conveys a request to capture at least one frame of a plurality of periodic frames. Step (B) may receive the periodic frames at a second circuit from the electro-optical sensor. Step (C) may discard a first frame of the periodic frames where the first frame precedes the request. Step (D) may store a plurality of active pixels in a second frame of the periodic frames in a memory where the second frame follows the request. The second circuit is generally a hardware implementation.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) process a digital image received from a camera sensor and (ii) convert the digital image after the processing. The converting generally uses a lookup table-based conversion that performs both (a) a color correction and (b) a tone correction.

Abstract: A method for compressing data samples using randomized quantization bins is disclosed. The method generally comprises steps (A) to (C). Step (A) may generate a size signal having a quantization step size corresponding to the data samples in an input signal using a compression circuit. The data samples generally reside in a range of numbers. Step (B) may generate the randomized quantization bins in the range based on a pseudorandom process. Step (C) may generate a plurality of quantized samples in a compressed signal by quantizing the data samples based on the randomized quantization bins.

Abstract: An apparatus having a server is disclosed. The server may be configured to (i) receive via a network a first clip of video generated by a camera, (ii) receive via the network first information to edit the first clip, (iii) receive via the network one or more segments of a second clip of video generated by the camera as identified by the first information and (iv) create a third clip of video by editing the segments according to the first information. The second clip is generally a higher resolution version of the first clip. The third clip may have the higher resolution.

Abstract: An apparatus including one or more motion sensors, a first circuit, and a second circuit. The one or more motion sensors may be configured to generate motion samples representing motion of a camera. The first circuit may be configured to record a plurality of the motion samples from the one or more motion sensors while capturing image data with the camera. The second circuit may be configured to transfer information about the motion of the camera based on the plurality of motion samples. The information about the motion of the camera may be transferred within a bitstream carrying the image data captured by the camera.

Abstract: A method of capturing a still frame is disclosed. The method generally includes the steps of (A) generating a plurality of initial frames with a sensor in response to an optical signal and (B) generating the still frame by combining the initial frames using a noise reduction technique.

Abstract: An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.

Abstract: An apparatus including a first register, a second register, and a control logic. The first register may be configured to store requests from a plurality of clients for a current cycle. The second register may be configured to store an indicator value indicating which of the plurality of clients received a grant in a previous cycle. The control logic may be configured to determine which of the plurality of clients having a request in the current cycle receives a grant based upon (i) a pointer value and (ii) the indicator value.

Abstract: A method for processing a source frame is disclosed. The method generally includes the steps of (A) generating a intermediate video frame by de-mosaicing the source frame, wherein (i) the source frame has a source resolution and has a source color space and (ii) the intermediate video frame has the source resolution and has an intermediate color space, (B) generating a video stream by compressing the intermediate video frame with a video compression technique and (C) generating a still picture from the source frame, wherein (i) the still picture has the source resolution and comprises a raw picture and (ii) generating the still picture occurs substantially simultaneously with generating the video stream.

Abstract: An apparatus including a local shared memory and a processor. The local shared memory and the processor may be connected as a circuit. The local shared memory may comprise a plurality of cache blocks. Each of the cache blocks generally corresponds to one of a plurality of panes of a current horizontal strip of a warped image region to be generated from unwarped image data retrieved from an external source. The circuit may be further configured such that each pixel of the unwarped image data retrieved from the external source is fetched only once. Each of the panes has associated tag information.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) receive a digital image from an electro-optical sensor, (ii) convert the digital image from a red-green-blue representation to a luminance-and-chrominance representation, (iii) generate a reduced noise representation of the digital image by reducing noise in the luminance-and-chrominance representation and (iv) generate a color corrected representation of the digital image by color correcting the reduced noise representation.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus comprising a classifier cache, a plurality of variable length decoder circuits and a core engine circuit. The classifier cache may be configured to store one or more compressed classifier streams. The plurality of variable length decoder circuits may each be configured to generate one or more uncompressed classifier streams in response to a respective one of the compressed classifier streams received from the classifier cache. The core engine circuit may be configured to detect one or more objects in a video signal by checking a portion of the video signal using the uncompressed classifier streams.

Abstract: An apparatus generally having a first memory, a second memory and a circuit is disclosed. The first memory may be configured to store a warp table. The warp table is generally accessed through a single data port of the first memory. The second memory may be configured to buffer an input image. The input image may have a plurality of input pixels arranged in two dimensions. The circuit may be configured to generate an output image by a warp correction of an input image. The warp correction may be defined by the warp table. The output image may include a plurality of output pixels. At least one of the output pixels maybe generated during each clock cycle of the circuit.

Abstract: A method of pixel correction is disclosed. The method generally includes the steps of (A) generating a plurality of pixel values from a sensor in response to an optical signal, (B) generating a temperature signal representing a temperature of the sensor and (C) generating a plurality of corrected values by applying a per-pixel correction model to the pixel values, wherein the per-pixel correction model is responsive to the temperature.

Abstract: An apparatus having a first circuit is disclosed. The first circuit may (i) receive an input signal from an electro-optical sensor and (ii) generate a compressed signal. The first circuit generally includes re-sampler circuits configured to process the input signal to generate output samples. Each output sample may be a linear combination of at least two input samples. Video processing may include at least two tasks among (a) generating a video signal by converting the input signal for an external video monitor, (b) generating a video signal by converting the input signal for a preview screen and (c) generating a video signal by resolution reduction of the input signal before compression. At least two re-sampler circuits may perform different tasks. Still processing generally includes a noise reduction of an input image of the input signal using at least one of the at least two re-sampler circuits.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: A method for processing a digital picture is disclosed. The method may include steps (A) to (C). Step (A) may generate a first picture by processing the digital picture using a first noise reduction technique in a circuit. Step (B) may generate a second picture by processing the digital picture using a second noise reduction technique. The first noise reduction technique may achieve a higher noise reduction than the second noise reduction technique. Step (C) may generate an output picture by combining the first picture and the second picture.