Patents Assigned to AmberWave Systems Corporation
  • Publication number: 20030227029
    Abstract: A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 11, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Westhoff
  • Publication number: 20030227013
    Abstract: A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 11, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 6649480
    Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-x Gex layer on the Si substrate, and a strained surface layer on said relaxed Si1-x Gex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-x Gex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: November 18, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Patent number: 6645829
    Abstract: A structure and method of fabricating an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: November 11, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzergald
  • Patent number: 6646322
    Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: November 11, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Publication number: 20030207571
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Application
    Filed: April 23, 2003
    Publication date: November 6, 2003
    Applicant: Amberwave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Publication number: 20030186073
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Application
    Filed: March 18, 2003
    Publication date: October 2, 2003
    Applicant: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6602613
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: August 5, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6593641
    Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: July 15, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzergald
  • Patent number: 6593191
    Abstract: A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: July 15, 2003
    Assignee: Amberwave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6594293
    Abstract: A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxailly growing a relaxed graded layer of InxGal-xAs at a temperature ranging upwards from about 600° C. with a subsequent process for planarization of the InGaAs alloy.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: July 15, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Eugene A. Fitzgerald
  • Patent number: 6589335
    Abstract: A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C. with a subsequent process for planarization of the InGaAs alloy.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: July 8, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Eugene A. Fitzgerald
  • Patent number: 6583015
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: June 24, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Publication number: 20030113948
    Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.
    Type: Application
    Filed: October 9, 2002
    Publication date: June 19, 2003
    Applicant: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6555839
    Abstract: A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embodiment, the FETs are interconnected to form an inverter.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: April 29, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Publication number: 20030057416
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 27, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • Publication number: 20030034529
    Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
    Type: Application
    Filed: October 8, 2002
    Publication date: February 20, 2003
    Applicant: Amberwave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Nicole Gerrish
  • Publication number: 20030030091
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: August 13, 2002
    Publication date: February 13, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 6518644
    Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: February 11, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6503773
    Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: January 7, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald