Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

Abstract: A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

Abstract: A method of determining power data of a system on a chip is disclosed. A plug-in module is provided for installation on the chip. The plug-in module is activated to take a snapshot of the data in power related registers of components on the chip when user provided software is executed on the system on a chip. The collected data is streamed to an external computing device. A spreadsheet of the collected register data may be displayed. A graphic representation of the collected register data may be displayed.

Abstract: A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.

Abstract: A power evaluation tool for a system on a chip is disclosed. The tool includes a power profiling plug-in module executed by a processor on the chip to collect a snapshot of register data of components on the chip associated with power consumption by the system during a certain time. The collected register data is streamed to an external computing device. A data parser module receives the streamed collected register data on the external computing device. A spreadsheet generator module creates a spreadsheet of the collected register data. An interface module displays a graphic representation of the collected register data on a display.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.

Abstract: Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

Abstract: A system for determining a power requirement for a device powered by a buck converter on a system on chip based on Time on pulses (Ton) is disclosed. A buck converter supplies output voltage to enable the device. The buck converter is driven by a Ton pulse generator generating Ton pulses to control charging of a load capacitor. A counter counts the Ton pulses during the supply of output voltage while the device is enabled. A controller is coupled to the counter and the buck converter. The controller determines the power requirement for the device based on the count of the Ton pulses. The power requirement may be used to adjust the trim value to change the width of the Ton pulses for greater energy efficiency.

Abstract: A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.

Abstract: In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

Abstract: A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

Abstract: A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.

Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

Abstract: A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.

Abstract: A buck converter may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

Abstract: A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

Abstract: An accelerometer and a linear resonant actuator (LRA) are mechanically coupled, such as by being mounted to the same circuit board. The output of the accelerometer is evaluated in order to select a drive frequency for the LRA. For example, the drive frequency may be varied while measuring the magnitude of acceleration induced by the LRA. The output of the accelerometer may further be used to perform a fitness tracking function, such as counting steps or detecting an activity level.