Abstract: A semiconductor package and electronic array in which the semiconductor packages of the array share a common substrate. The substrate has a plurality of sets of contacts with each set of contacts receiving contacts of a semiconductor chip. Each chip and set of contacts is surrounded by a closed length of bond receptive material. A heat dissipation member is attached to each chip by means of a heat conductive plate, and an annular ring is bonded to each heat dissipation member and to the closed length of bond receptive material to hermetically seal the chip.

Abstract: Disclosed is a primary data processing system comprised of, for example, a main store, a storage unit, an instruction unit, an execution unit, a console unit and a channel unit for performing primary system programs. The console unit includes a secondary digital computer for performing secondary programs which functions to observe and/or alter the primary system. The functions performable by the secondary system include altering the primary system control state, causing primary commands to be executed, controlling primary data and addresses, and scanning out primary information. The console is connected through a command bus, an address bus and a data bus to the controls and data paths of the channel unit, of the instruction unit and of the storage unit.

Abstract: Disclosed is a primary data processing system comprised of, for example, a main store, a storage unit, an instruction unit, an execution unit, a console unit and a channel unit for performing primary system programs. The console unit includes a secondary digital computer for performing secondary programs which functions to observe and/or alter the primary system. The functions performable by the secondary system include altering the primary system control state, causing primary commands to be executed, controlling primary data and addresses, and scanning out primary information. The console is connected through a command bus, an address bus and a data bus to the controls and data paths of the channel unit, of the instruction unit and of the storage unit.

Abstract: A data processing system having a principal apparatus, such as a programmable large-scale data processing system, and a secondary apparatus. The secondary apparatus performs fault detection and analysis on the principal apparatus. The secondary apparatus under control of a secondary program and independently from the principal apparatus, accesses information from different points, such as latch circuits, throughout the principal appartus. The accessed information is utilized by the secondary apparatus to form an actual checksum having a value determined by the accessed information. The actual checksum thus formed is compared with an expected checksum provided from storage by the secondary apparatus. If the actual and expected checksums are different, a fault condition is indicated. An analysis of selected subsets of points in the primary apparatus is made using a compacted scan composed of the values of the selected subset of points.

Abstract: Package for an LSI chip having a plurality of contact pads comprising a carrier and a cover. The carrier is formed of a base of an insulating material and has a generally planar area for receiving the chip. A cooling stud is mounted on the base and can be provided with one or more removable cooling fins. The stud is mounted on the base opposite the area for receiving the chip. Spaced leads are carried by the base and have outer extremities which extend beyond the base in a direction away from the chip and are free of the carrier and have inner extremities which are in close proximity to the area for receiving the chip. A grounding bus is carried by the carrier to facilitate electrical checking of the package.

Abstract: Disclosed is a data processing system including a channel unit which services a plurality of channels. The channel unit is connected between the data processing system and the control units which control the operations of I/O devices. The channel unit includes one processor for controlling transfers between channel storage and system storage and having another processor for controlling transfers between input/output devices and channel storage.

Abstract: A high density multilayer printed circuit card assembly having plated through holes in electrical contact with the layers of conducting metal. The card is provided with bonding pads in contact with the plated through holes whereby wiring may be selectively utilized to form interconnections for components carried by the card. Signal lines are brought to the surface so that they can be interrupted and changes be made by wiring. Components of various types are arranged in rows to facilitate cooling.

Abstract: LSI chip construction having a semiconductor body with a plurality of transistors formed in the semiconductor body in a predetermined pattern and a plurality of resistors formed in a semiconductor body in a predetermined pattern. Means is provided which includes two layers of metallization having input and output pads adjacent the outer perimeter of the body and contacting said transistors and resistors to form a plurality of emitter-follower circuits with certain of the emitter-follower circuits being made up of larger transistors and being located near the perimeter of the chip and near the input-output pads. The other emitter coupled circuits are clustered in groups to form an array of such groups with each of the groups being capable of containing a plurality of logic circuits.

Abstract: A data processing system where transfers of information are made between I/O devices and system storage through channels is a channel unit having common apparatus shared among all the channels. The common apparatus includes a sequentially accessed state memory and a plurality of processors. The state memory includes a memory location for each channel. The processors have access to different parts of the state memory and perform functions in response to stored information. A data access processor controls transfers between system storage and the channel unit. A controller interface processor controls transfers between the channel unit and I/O devices. The quantity of information to be transferred for each channel is stored in the state memory. Each time a portion of the total transfer is completed, a count field in the state memory is updated.

Abstract: Disclosed is a method and apparatus for program event recording in a data processing system and is used, for example, in debugging programs. A program event occurs whenever an address in the data processing system falls within a range between a control lower address (DTCL) and a control upper address (DTCU). The system detects a program event without degrading system performance using carry-lookahead adder structures which implement four inequality relationships.