Abstract: Current protection in integrated circuit having multiple pads. Different types of current protection structures may be associated with different pads. A common current discharge or charge path may be used to provide current to or draw current from various of these heterogenic current protection structures. Since a common current discharge or charge path is used, the metallization used to formulate a discharge solution is significant simplified. Additionally, the protection structures may be provided with selectively conductive regions that are approximately radially symmetrical around the circumference of the pad. Accordingly, if the protection structures are slightly off center with respect to the bond pad (due to, for example, mask alignment error), the error in the amount of active region around the circumference of the pad is at least partially averaged out.

Abstract: Digital delay locked loops which generate fixed angle delayed (e.g., quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature delay elements is calculated based on the number of delay elements needed to provide one or more cycles of delay, and adjusted to reflect system clock delay. The digital delay locked loop also acquires a locked state quickly by sampling more frequently before acquiring the lock than after. Furthermore, jitter is reduced by introducing hysteresis into the sampling process, and by disabling the delay element adjustment process during jitter sensitive times. Lock stability is improved by introducing hysteresis into the lock detection process.

Abstract: One embodiment of the present invention provides for a master or universal base and base tooling which addresses the general purpose Structured ASIC requirements. Another embodiment of the present invention provides for a common set of base tooling from which the master/universal base is created as well as additional custom bases with customized selection and quantity of embedded Platform ASIC functions. Embodiments can utilize conventional Structured ASIC architecture and processing and are compatible with traditional probing and packaging.

Abstract: Calibration of a sensor circuit that includes a sensor, a temperature measurement circuit and a signal processing path. The sensor senses a physical parameter to be measured and generates an electrical sensor output signal representing the physical parameter. The temperature measurement circuit outputs a measured temperature. The signal processing path is coupled to the sensor so as to receive the electrical sensor output signal and use the measured temperature to compensate for temperature variations in the electrical sensor output signal. During calibration, the output voltage of the signal processing path is measured at multiple temperatures, and at multiple values of the physical parameter being measured at each temperature while the signal processing path is disconnected from using the measured temperature of the temperature measurement circuit.

Abstract: A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region of the first carrier type, and a source region of the first carrier type that is laterally separated from the channel region by a second RESURF region of the first carrier type. Regions of the first carrier type may also be disposed laterally adjacent to the source and drain regions on the opposite lateral side as compared to the RESURF regions. This configuration improves the reverse bias breakdown voltage of the transistor.

Abstract: A track and hold (or sample and hold) offset compensated amplifier circuit that performs offset compensation in response to a comparison of sign (or sign and value) of the current forced to the output terminal of operational amplifier in order to keep it at the potential of holding capacitor during the holding phase. Based on this comparison, the comparison circuit increases or decreases the voltage differential applied between the positive and negative input terminals of the operational amplifier depending on whether the comparison circuit detects that the current forced to the output terminal of the operational amplifier is positive or negative. During the holding phase, negative feedback is disconnected, and the positive and negative input terminals of the operational amplifier are connected.

Abstract: A differential voltage signal (LVDS) driver circuit and/or a Current Mode Logic (CML) driver circuit. The circuit includes two current switches, each coupled to a corresponding input node. In a complementary manner, when a differential signal is applied across the input nodes, one current switch is open, while the other current switch is closed, and vice versa. A current allocation component allocates current between the two input current switches such that, when the first current switch is closed and the second current switch is open, increasing current is allocated through the first current switch and the intervening current path between the current allocation component and the first current switch, and vice versa. The circuit includes complementary pre-emphasis and/or current-aided pre-emphasis mechanisms that boost differential output transmission edges.

Abstract: A direct conversion circuit that includes an in-phase and quadrature-phase feedback path that reduces Direct Current (DC) offset. Each feedback path includes a compensating mixer that generates an error correction voltage that is passed through a loop gain circuit and an integrator. The integrated signal is applied to the output of a low pass filter that operates on the down-converted baseband signal. The direction conversion circuit may not only down convert the received modulated signal using a down-converting mixer into a baseband signal, but also, after performing a passive low pass filtering to remove higher-order components, performs up-conversion of the baseband signal using an up-converting mixer. This allows active elements operating on the up-converted signal to introduce less 1/f noise.

Abstract: Methods and systems using Pade' Approximant expansion ratios provide mappings between nonlinear sensors and a more linearized output domain. In one embodiment (a) a variable gain amplifier receives a supplied input signal, the amplifier has at least a first input terminal, an output terminal, and a gain control terminal; (b) a first summer coupled to the output terminal of the variable gain amplifier adds in a first offset signal; (c) a first multiplier coupled to an output of the first summer receives a proportional feedback factor signal and correspondingly generates a multiplied feedback; (d) a second summer coupled to an output terminal of the first multiplier adds in a corresponding second offset signal; and (e) a second multiplier coupled to an output of the second summer receives a gain factor signal and generates a multiplied gain signal; where the gain control terminal of the variable gain amplifier is operatively coupled to an output terminal of the second multiplier.

Abstract: A low power analog-to-digital channel includes a decimation filter coupled to a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately a integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.

Abstract: A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate glass is deposited on the first layer of undoped silicate glass. This combination is then densified by applying a temperature to the combination that is sufficient to densify the layer of phospho-silicate glass, while being below the glass flow temperature. After densification, a second layer of undoped silicate glass is deposited on the densified layer of phospho silicate glass. Finally, the upper surface of the second layer of undoped silicate glass is polished using a chemical mechanical polishing process. The result is a dielectric layer of high density and low stress, and that reduces soft errors and defects.

Abstract: Systems, devices, and methods are provided to inhibit apparent amplitude modulation in non-linear processing that causes distortion in a processed signal. One aspect of the invention includes a hearing aid. The hearing aid includes a microphone to receive an input signal, a speaker to reproduce the input signal, and a processor. The processor processes the input signal using a gain. The processor includes an inhibitor, which inhibits distortions, and an adjuster, which adjusts the gain. The inhibitor acts to smooth an envelope of the input signal to inhibit undesired modulation. The adjuster adjusts the gain if the envelope is either above or below a threshold. The hearing aid further includes a compression recapture system to supply the compressed portion of the input signal to more closely reproduce the actual input signal.

Abstract: A direct conversion circuit that not only down-converts the received modulated signal using a down-converting mixer into a baseband signal, but also, after performing a passive low pass filtering to remove higher-order components, performs up-conversion of the baseband signal using an up-converting mixer. Active elements such as highly sensitive amplifiers do not operate on the baseband signal itself, but on the up-converted version of that baseband signal, thereby reducing the 1/f noise introduced by those active elements. The downstream circuitry after the up-conversion may be coupled by intervening capacitors since the downstream circuitry is operating on a higher frequency signal. Accordingly, the DC offset introduced by the downstream active elements is reduced.

Abstract: Method and system for real-time speech recognition is provided. The speech algorithm runs on a platform having an input-output processor and a plurality of processor units. The processor units operate substantially in parallel or sequentially to perform feature extraction and pattern matching. While the input-output processor creates a frame, the processor units execute the feature extraction and the pattern matching. Shared memory is provided for supporting the parallel operation.

Abstract: A method and system for synthesizing audio speech is provided. A synthesis engine receives from a host, compressed and normalized speech units and prosodic information. The synthesis engine decompresses data and synthesizes audio signals. The synthesis engine can be implemented on a digital signal processing system which can meet requirements of low resources (i.e. low power consumption, lower memory usage), such as a DSP system including an input/output module, a WOLA filterbank and a DSP core that operate in parallel.

Abstract: A receiver circuit that includes a direct conversion receiver that receives a modulated signal, and generates an in-phase differential signal and a quadrature-phase differential signal. The receiver circuit includes an in-phase branch that processes the in-phase differential signal, and a quadrature-phase branch that processes the quadrature-phase differential signal. Each branch includes an amplifier and a summer. The amplifier is configured to receive and amplify the respective in-phase or quadrature-phase differential signal. The summer receives the resulting amplified differential signal and sums the signals to generate a single signal. A log amplifier receives the summed in-phase and quadrature-phase signal, and generates an RSSI signal that is proportional to the log of the difference between the two summed signals. The data may then be extracted based on the amplitude of the RSSI signal.

Abstract: An adaptive signal processing system for improving a quality of a signal. The system includes an analysis filterbank for transforming a primary information signal in time domain into oversampled sub-band primary signals in frequency domain and an analysis filterbank for transforming a reference signal in time domain into oversampled sub-band reference signals. Sub-band processing circuits process the signals output from the filterbanks to improve a quality of an output signal. A synthesis filterbank can combine the outputs of the sub-band processing circuits to generate the output signal.

Abstract: A closed loop DC-to-DC converter circuit that includes an open loop DC-to-DC converter circuit configured to provide charge on its output terminal. A voltage-controlled inverse-resistance component is coupled to the output terminal of the open loop DC-to-DC converter circuit, such that the greater the voltage differential across the component, the lower the resistance provided by the component. A feedback system provides a signal to a control terminal of the open-loop DC-to-DC converter circuit that is dependent on the current provided through the voltage-controlled inverse-resistance component. Specifically, the signal provided by the feedback system causes the open loop DC-to-DC converter circuit to generate more current on the output terminal when there is less current passing through the voltage-controlled inverse-resistance component, and less or no current on the output terminal when there is more current passing through the voltage-controlled inverse-resistance component.

Abstract: An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.

Abstract: An operational amplifier with two differential pairs coupled to different current sources. The gate terminals of the transistors in the first differential pair are used as input terminals providing common mode input for most of the rail-to-rail voltage. The bulk terminals of the transistors in the second differential pair are used as input terminals providing common mode input for the remainder of the rail-to-rail voltage to thereby accomplish full rail-to-rail common mode. By using the bulk terminals of the field effect transistors in the second differential pair, rather than the gate terminals, as the input terminal, the operational amplifier may be constructing in a single well, thereby being compatible with standard digital CMOS processes. Alternatively, the bulk-driven transistors may be replaced with gate-driven depletion type transistors. The high voltage transistors in the output stage further reduce the offset voltage of the operational amplifier.