Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: A programmable voltage reference circuit that includes a current-to-voltage converter circuit, a voltage-to-current converter circuit, and a floating gate. The current-to-voltage converter circuit has two current input terminals and a voltage output terminal. The voltage-to-current converter circuit has two voltage input terminals and two current output terminals. The two current output terminals are each coupled to a corresponding current input terminal of the current-to-voltage converter circuit. A floating gate device has one terminal coupled to a fixed voltage supply, and one terminal coupled to an input terminal of the voltage-to-current converter. The other input terminal of the voltage-to-current converter is coupled to the voltage reference output terminal of the programmable voltage reference circuit. Also, the voltage output terminal of the current-to-voltage converter circuit is coupled to the negative voltage input terminal of the voltage-to-current input circuit.

Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduce capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: An EEPROM memory cell that includes two floating gate transistors. Each of the drain terminals of the transistors is coupled to a corresponding differential bit line. The source terminal of both transistors are coupled to a common current source or sink. Each of the control gate terminals are coupled to a corresponding word line, which may be the same as or different than the corresponding word line that the other control terminal is connected to. The floating gate transistor may be five-terminal devices that include an additional well terminal. In that case, a different set of bit lines is used to program the EEPROM memory cell as are used to read the EEPROM memory cell. While the drain terminals are coupled to the differential read bit lines, each of the well terminals is coupled to a corresponding differential program bit line.

Abstract: Amplitude detection of a baseband electrical signal. The detection may be performed by performing full wave rectification on both an in-phase portion of the electrical signal, as on a quadrature-phase portion of the electrical signal. The output signal may be generated by summing the rectified in-phases signal and the rectified quadrature-phase signal. The peak amplitude of the output signal may then be used to determine the amplitude of the original baseband signal.

Abstract: A direct conversion receiver is disclosed that converts RF signal into corresponding quadrature baseband signals without requiring conversion through an intermediate frequency. The direct conversion receiver abates local oscillator leakage, increases dynamic range and increases RF selectivity as compared to conventional direct conversion circuits. The circuit includes an in-phase branch and a quadrature-phase branch, each branch including two mixers instead of the conventional one. Each mixer is provided with balanced control signals that include a primary control signal and a complementary control signal. For each branch, the signals from the mixer pass through an operational amplifier and a low pass filter to extract the corresponding baseband signal component.

Abstract: An enhanced output impedance current mirror in which the operational amplifier includes a set of four MOSFETs having a common gate that is connected to a drain terminal of one of the differential pairs. Two of the MOSFETs reside in parallel in the current path of each of the MOSFETs of the differential pair. The differential pair MOSFET that has its drain terminal connected to the common gate also has a gate terminal that is connected to the common node between the two other MOSFETs in its current path.

Abstract: A runtime programable RS decoder that can operate on multiple pieces of data during one clock cycle in order to generate, reduce, and evaluate polynomials involved in the decoding of an RS code, and which allows a user to choose the RS code after the circuit has been implemented.

Abstract: A bandgap reference that generates a temperature stable DC voltage by using a corrective current. The corrective current is generated by a series of differential pairs that are controlled by both positive temperature shift gate voltage on one transistor, as well as a negative temperature shift gate voltage on the other transistor. As temperature changes and crosses the crossing point at which the current is split evenly through both transistors, the current change is more abrupt. The crossing points of each of the differential pairs may be appropriately selected so as to generate a high resolution corrective current. The various current contributions are summed to form the total corrective current, which tends to be quite accurate due to the abrupt crossing points. The corrective current is then fed back into the circuit so as to compensate for much of the temperature error.

Abstract: A bandgap voltage reference uses multiple PTAT voltage reference circuits (also called PTAT sources) coupled in series to generate a final PTAT voltage. A current-biased base-emitter region of a bipolar transistor is coupled between the final PTAT voltage and an output terminal of the bandgap voltage reference so as to add the base-emitter voltage to the final PTAT voltage to thereby generate a stable bandgap voltage reference. By using multiple PTAT voltage reference in series, the need for a resistor ratio is reduced (or even eliminated) thereby reducing the size of the resistors that generate the resistor ratio (or eliminate the need for the resistors entirely).

Abstract: Transconveyance amplifiers, and more specifically charge transfer amplifiers, are included in analog-to-digital converters. Transconveyance amplifiers are used in averaging and interpolation circuits that facilitate converting an analog signal into a meaningful digital representation of the analog signal. Due to the characteristics of charge transfer amplifiers power dissipation in averaging and interpolation circuits is significantly reduced. Coupling capacitors associated with charge transfer amplifiers are utilized as analog sample and hold circuits for holding an analog signal while fine reference voltages settle. Thus, the need for separate sample and hold circuits is eliminated. A novel timing scheme allows an increased number of clock partitions for fine reference voltages to settle, thus providing for increased operational frequency.

Abstract: A charge transfer amplifier that performs amplification without a selective coupling to a precharge reference voltage. In lieu of the selective precharge coupling, the drain of the PMOS transistor is selectively coupled to Vss during the reset and precharge phases. In addition, the drain of the NMOS transistor is selectively coupled to Vss during the reset phase, and is selectively coupled to Vdd during the precharge phase. The drain of the PMOS transistor is capacitively coupled through a first intermediate capacitor to the output terminal of the charge transfer amplifier. The drain of the NMOS transistor is capacitively coupled through a second intermediate capacitor to the output terminal. During the amplify phase, the drains of the NMOS and PMOS transistor are permitted to float except for any charge flow through the respective transistor.

Abstract: A memory initialization circuit includes one or more duplicated pairs of bit lines, which may be used to initialize the memory cells of a memory array to different logical values. When an initialization signal is asserted on the initialization circuit, the individual bit lines in the pair of bit lines are set to opposite logical values, for instance setting one bit line to a logical zero and the other to a logical one. This occurs without regard to external data values received by the circuit. When the initialization signal is removed, individual bit lines in a duplicated pair carry identical values, which may be equal to external data values that are received by the circuit. Thus, after initialization, memory cells function as if duplicated pairs were not included in the circuit. A memory array may be initialized to a predetermined pattern by coupling different combinations of memory cells to different bit lines from duplicated pairs.

Abstract: A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block.

Abstract: A charge transfer amplifier includes a first stage charge transfer amplifier coupled to a positive capacitive feedback mechanism. The positive capacitive feedback mechanism is attached to the output terminal of a first stage charge transfer amplifier. This reduces the capacitance viewed at the output terminal of the first stage charge transfer capacitor thus increasing the overall gain of the charge transfer amplifier. The positive capacitive feedback mechanism includes a second stage amplifier having an output terminal capacitively coupled back to the output terminal of the first stage charge transfer amplifier. The coupling of the positive capacitive feedback mechanism to the charge transfer amplifier allows for enhanced amplifier gain while still retaining the beneficial characteristics of charge transfer amplifiers generally.

Abstract: A current reference circuit provides a reference current that has a controlled temperature coefficient and is relatively stable with supply voltage fluctuations. The reference leg includes a series of MOS transistors including at least one PMOS transistor that is electrically closer in the series to a high voltage source, at least one NMOS transistor that is electrically closer in the series to the low voltage source. The series composite resistor comprises at least two resistors coupled in series within the current path. The size of the resistors may be designed so as to lower the temperature dependency of the circuit. A bipolar transistor is also coupled in the reference leg. The mirror leg is similar to the reference leg except that no series resistor is provided, and the emitter area of the bipolar resistor in the reference leg is larger than the emitter area of the bipolar transistor in the mirror leg.

Abstract: A bandgap voltage reference circuit includes a current source and a bipolar transistor that are coupled together such that current from the current source passes through the bipolar transistor to a low voltage source such as ground. A composite resistor is coupled in series between the current source and the bipolar transistor. The composite resistor of this voltage reference leg of the circuit is composed of at least two component resistors that may be fabricated so as to adjust the temperature coefficient of the bandgap voltage reference as a whole.