Abstract: A semiconductor package having a light, thin, simple and compact structure including outer leads having a minimum length and a resin encapsulate having a minimum volume. The semiconductor package includes a package body, a semiconductor chip mounted on a central portion of the body, inner and outer leads bonded to a peripheral portion of an upper surface of the body by an insulating layer in such a manner that the leads are supported on the body, conductive wires or bumps for electrically connecting the inner leads to the semiconductor chip, a resin encapsulate for encapsulating the semiconductor chip, the conductive wires or bumps and the inner leads. Each outer lead has an end positioned at a level higher than an upper surface of the semiconductor chip so that a boundary portion defined between the associated outer and inner leads serves as a barrier for the resin encapsulate. The end of each outer lead is exposed outside the resin encapsulate and extending to a peripheral edge of the body.

Abstract: A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

Abstract: A method of manufacturing an alumina-silicon carbide nanocomposite having particular application to improved ball bonding capillaries of a wire bonding device produces a structure with a 93-98 volume percent of .alpha.-alumina having an average diameter of 0.1-0.3 .mu.m, a 2-7 volume percent of .beta.-silicon carbide having an average diameter of 0.1-1.5 .mu.m, a bending strength of 340-550 Mpa, and a toughness of 3.3-4.1 Mpam.sup.1/2.

Abstract: A unit printed circuit board (PCB) carrier frame used in the fabrication of a heat sink-attached ball grid array (BGA) semiconductor packages and a method for BGA semiconductor packages using the unit PCB carrier frame. The unit PCB carrier frame has a plurality of die pads each defined at its peripheral edges by elongated slots formed at a strip or reel-shaped frame member. For the fabrication of heat sink-attached BGA semiconductor packages, unit PCBs are bonded to the die pads of the unit PCB carrier frame. Accordingly, the bending of the packages is minimized even when they pass through subsequent processes requiring a high temperature. As a result, it is possible to obtain a maximum number of unit PCBs from a PCB panel, thereby achieving an improvement in productivity.

Abstract: A wafer map conversion method capable of converting a format file, which includes data about a wafer obtained by category grades through a wafer testing device and all information associated with the wafer in accordance with a certain format, into a configuration file or standard file which can be practically applied to a die bonding device, thereby easily checking the content of the process through a processing mode translated from the configuration file or standard file. Practically, the die bonding process for good-grade dies by grade levels can be achieved based on BCE data. It is also possible to perform the die bonding process in accordance with a certain map format without requiring any test for the wafer memory and dies. Only selected dies can be processed without requiring an alignment and test for every die. Accordingly, a great improvement in the process quality is obtained. An improvement in yield in processing rate (UPH) is also achieved.

Abstract: A socket for a ball grid array chip carrier package containing a die which is electrically interconnected. Individual spring elements in the socket are utilized for interconnecting each ball of the ball grid array. The individual spring elements provide upward pressure against individual sections of a substrate in direct contact with the balls of the ball grid array. The individual sections of the substrate are formed into individual beam members that are permitted to flex in response to pressure from the underlying spring elements.

Abstract: A thermoplastic chip carrier cavity package for one or more semi-conductor integrated circuit chips. A circuit substrate is formed of a suitable thermoplastic such as PPS or LCP. A casing is further formed atop the substrate with the casing being made of the suitable thermoplastic and being chemically fused to a portion of the circuit substrate to create a moisture seal therebetween. An encapsulant for filling the cavity within the casing and a lid may also be utilized to further secure and seal the chip mounted therein from moisture.

Abstract: A heat sink-integrated semiconductor package is fabricated by a characteristic method comprising the steps of dispensing a liquid epoxy resin over at least the bare surface of a heat sink mounted with a semiconductor chip, curing said dispensed liquid epoxy resin to form a first encapsulating part so as to prevent delamination at the interface between said heat sink and said semiconductor chip, molding a mold compound to form a second encapsulating part to protect said package from the external environment. The semiconductor package of the present invention, the first encapsulating part is of stronger bonding strength than the second encapsulating part, so that the delamination phenomenon at the interface between heat sink and semiconductor chip can be prevented or relieved efficiently.

Abstract: A printed circuit board (PCB) having an epoxy barrier disposed around its throughout slot in a semiconductor chip mounting region, and a BGA semiconductor package using such a PCB, thereby exhibiting a high moisture discharge characteristic. The epoxy barrier includes a copper layer and a solder resist layer both disposed around the throughout slot and is defined by a groove which is disposed around the throughout slot while spacing apart from the periphery of the throughout slot by a desired distance. Alternatively, the epoxy barrier includes a solder resist layer formed to a desired width around the throughout slot on the uppermost layer laminated on the PCB. By virtue of the epoxy barrier, the throughout slot is not closed by epoxy resin coated over the PCB. As a result, it is possible to externally discharge moisture which expands in the PCB upon carrying out a series of processes for the fabrication of the package at a high temperature or mounting the package on a mother board.

Abstract: This invention is related to providing a bonding method for flip chips in which the circuit part is oriented to be face-down on a substrate after bonding bumps are formed on the semiconductor chip namely, forming Au bumps by Au wire ball bonding employing a wire ball bonding device onto aluminum bond pads of the semiconductor chips; coating the Au bumps with Sn/Pb alloy bumps also by wire ball bonding using a wire ball bonding device; with or without re-forming the Sn/Pb alloy bumps into a desired ball-shape by performing a heat treatment in a furnace after an activation solvent is applied to the Sn/Pb alloy bumps; and bonding (by the heat treatment in the furnace) the substrate to the coated bumps containing chip by a heat treatment in the furnace.

Abstract: A BGA (ball grid array) semiconductor package with improved heat dissipation and dehumidification effect is disclosed. The above BGA package is provided with an open through slot on the chip mounting portion of the printed circuit board and/or the heat sink. The above through slot is occluded by neither the heat conductive epoxy resin nor the solder mask but is simply opened, thus directly exposing the bottom surface of the semiconductor chip to the outside of the package and effectively performing heat dissipation and dehumidification without causing any pop corn phenomenon during the dehumidification reflow. The size of the open through slot is not larger than the semiconductor chip. The open through slot is selected from among a rectangular slot, a large circular slot, a plurality of small circular slots, a radial slot, a cross slot or any combination thereof.

Abstract: A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a "keyhole" cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region.

Abstract: A lead frame for semiconductor packages is disclosed. In the lead frame, some of the inner leads in the four sides are extended and provided with connection bars on their inside ends. Alternatively, diagonally arranged tie bars of the lead frame are extended and provided with a rectangular guide ring on their inside ends. The connection bar or guide ring functions as a dam for restricting possible overflow of adhesive, which adhesive is applied on the heat sink for bonding a semiconductor chip to the heat sink. The lead frame of the invention also prevents waste of expensive tape by letting the adhesive tape adhere only to the connection bars or to a given portion of the guide ring when mounting the lead frame to the heat sink and makes it possible higher integration of semiconductor chip by making connection bar and guide ring from the lead or the tie bar.

Abstract: A method for checking wire bonding result of a ball grid array (BGA) package is disclosed. An electroconductive metal layer of gold or copper is grounded on a chip bonding portion of a printed circuit board (PCB) of the BGA package as well as on a passage extending between the chip bonding portion and the gate of the PCB. After a wire bonding step, a probe and a capillary of a wire bonding checking system contact with the gate and with a semiconductor chip respectively. Thereafter, an electric current is sent to the BGA package from the checking system so as to check whether the BGA package sends the electric current therethrough. When there is neither a lift bond nor a missing wire in the BGA package, the package will send the current. However, when there is either a lift bond or the missing wire in the BGA package, the package will not send the current.

Abstract: A BGA (ball grid array) semiconductor package with a ring-type heat sink is disclosed. In the above package, the heat dissipating area is enlarged by extending the edge of a chip mounting die paddle formed of a copper or copper alloy layer to the outside of the package. The ring-type heat sink is attached to the extended portion of the die paddle such that the heat sink surrounds the encapsulant of the package. The above BGA package thus directly and effectively dissipates the chip's heat through the heat sink with high thermal conductivity. A plurality of plated through holes may be formed on the chip mounting portion of the PCB of the above package. The BGA package with both the ring-type heat sink and the PTHs, the heat dissipating effect of the package is further improved.

Abstract: A packaged semiconductor die includes a heat sink having a locking feature that interlocks with the encapsulant encapsulating the die to minimize or eliminate delamination of the encapsulant from the heat sink. A surface of the heat sink can be exposed to the exterior of the encapsulant. The invention applies broadly to packaged integrated circuits including multichip modules and hybrid circuits, as well as to packaged transistors. In one embodiment of the invention, a locking moat has a cross-sectional shape that has, at a first distance beneath a locking surface of the heat sink, a width that is larger than a width at a second distance beneath the locking surface, the second distance being smaller than the first distance. The locking moat can have, for example, a "keyhole" cross-sectional shape or a circular cross-sectional shape. The locking moat can be formed by, for example, stamping or chemical etching. In another embodiment of the invention, the locking feature is a locking region.

Abstract: Two interdigitated comb-shaped fixed voltage buses such as a power bus and ground bus, in the form of metallization are provided substantially encircling of an integrated circuit die in an integrated circuit package or other integrated die assembly. Any selection of bonding pads on the die and metallization leads in the assembly may be connected to the fingers of either bus. The length of wire bond or TAB connections and the area occupied by the buses is minimized by the interdigitated geometry of the buses.

Abstract: A chip mounting plate construction of lead frames for semiconductor packages which provides a chip mounting plate having a greatly reduced area to obtain a small bonding area between the chip mounting plate and a semiconductor chip mounted on the chip mounting plate, thereby capable of minimizing thermal strain generated at the chip mounting plate due to a thermal expansion thereof. The chip mounting plate is constructed to have a smaller area than the semiconductor chip, to have a central opening, or to have recesses.

Abstract: A thermally enhanced chip carrier package with a built-in heat sink for semi-conductor integrated circuit chips. A circuit substrate is formed of a suitable thermoplastic such as PPS or LCP with a center opening and a metal attachment ring for attaching a heat sink to either the top or bottom thereof with solder. A casing is further formed on the substrate outwardly of the aperture and the heat sink mounted thereacross, the casing being comprised of the suitable thermoplastic and being chemically fused to a portion of the circuit substrate to create a moisture seal therebetween. An encapsulant for filling the cavity within the casing and a lid may also be utilized to further secure and seal the chip mounted to the heat sink secured therein.

Abstract: Method and circuit board structure for leveling the tops of solder balls of a BGA semiconductor package is disclosed. In order to level the solder balls, the sizes of solder ball lands used for welding the solder balls to the circuit board are controlled in accordance with portions of the circuit board. The invention thus achieves the coplanarity of the solder balls regardless of thermal bending of the plastic body and circuit board of the BGA semiconductor package. In an embodiment, a plurality of solder ball lands having different sizes are formed on the circuit board prior to forming the solder balls on the lands. In another embodiment, a plurality of solder ball lands having the same size are formed on the circuit board prior to forming an insulating mask on the circuit board in order to form differently-sized exposed inside portions of solder ball lands.