Abstract: A system and method for operating a high dynamic range analog front-end receiver for long range LIDAR with a transimpedance amplifier (TIA) include a clipping circuit to prevent saturation of the TIA. The output of the clipping circuit is connected via a diode or transistor to the input of the TIA and regulated such that the input voltage of the TIA remains close to or is only slightly above the saturation threshold voltage of the TIA. The regulation of the input voltage of the TIA can be improved by connecting a limiting resistor in series with the diode or transistor. A second clipping circuit capable of dissipating higher input currents and thus higher voltages may be connected in parallel with the first clipping circuit. A resistive element may be placed between the first and second clipping circuits to further limit the input current to the TIA.

Abstract: The present disclosure relates to a gate driver system suitable for driving the gate voltage of one or more transistors. The gate driver system is configured to operate in a first state when the current conducted by the transistor is relatively low and in a second state when the current conducted by the transistor is relatively high. In the second state, the gate voltage is set such that the source voltage at the transistor establishes a lower voltage across a source-driven load than is the case when operating the first state, thereby reducing the level of power consumption in the load during second state operation.

Abstract: Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.

Abstract: In an example, a device for controlling an electronic switch between a power supply and a load includes a first device pin configured to be in communication with the electronic switch, a sensing circuit configured to be connected to an input voltage and to measure a current to the load, a control circuit configured to be in communication with the sensing circuit and the electronic switch, the control circuit configured to use a current limit signal to control operation of the electronic switch, and a current limit circuit configured to be in communication with the control circuit, the current limit circuit configured to generate the current limit signal representing a current limit and automatically adjust the current limit signal in response to a change in at least one of the input voltage and an output voltage.

Abstract: Optically isolated micromachined (MEMS) switches and related methods are described. The optically isolated MEMS switches described herein may be used to provide isolation between electronic devices. For example, the optically isolated MEMS switches of the types described herein can enable the use of separate grounds between the receiving electronic device and the control circuitry. Isolation of high-voltage signals and high-voltage power supplies can be achieved by using an optical isolator and a MEMS switch, where the optical isolator controls the state of the MEMS switch. In some embodiments, utilizing optical isolators to provide high voltages, the need for electric high-voltage sources such as high-voltage power supplies and charge pumps may be removed, thus removing the cause of potential damage to the receiving electronic device. In one example, the optical isolator and the MEMS switch may be co-packaged on the same substrate.

Abstract: The present disclosure provides an improved Rogowski-type current sensor. In order to allow the sensing coil and the compensation wire to overlap, the sensor is produced using two boards. The current sensing coil is provided on one board, and the compensation wire is provided on another board. The coil and the wire are arranged such that they at least partially overlap, and ideally the compensation wire is formed entirely within the area defined by the coil, albeit in a different plane. This arrangement makes the current sensor far better at rejecting interference than prior art PCB arrangements. In addition, the coil may be formed on a two-sided board. The board has upper radial elements formed on an upper surface, and lower radial elements formed on lower surface. The radial elements are connected using vias formed in the board. The upper radial elements are arranged in a first plane, and the lower radial elements are formed in a second parallel plane.

Abstract: A dither is an uncorrelated signal, usually pseudo-random noise injected into the input of an ADC such that a given input value of the wanted signal becomes spread over a plurality of codes. This reduces the effect of DNL and also smooths the integral non-linearity (INL) response of the ADC. The advantages of introducing dither could be obtained without having to perturb the signal input to the ADC. This avoids the introduction of additional components in the ADC. The dither can be applied to the components used to form a residue of the ADC stage within a pipelined converter. For example, a dither can be applied solely to a DAC part or different dithers can be applied to a ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.

Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

Abstract: SPI Round Robin Mode for Single-Cycle MUX Channel Sequencing. SPI round robin mode is an SPI mode applicable for MUX devices control. It allows the MUX output to connect to the next input channel sequentially in just one clock cycle. Configurations can be made such as: clock edge to use (rising/falling), ascending/descending channel sequence, and enabling/disabling the channels to go through. The device supersedes an ADC with built in sequencing and is applicable to multiplexing, switching, instrumentation, process control and isolation application—while retaining SPI device control and operation.

Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

Abstract: A duty cycled voltage reference circuit is turned on and off synchronously with the operation of a second, reference-consuming, duty-cycled circuit to which it supplies a reference. When the reference consuming circuit no longer has need of the reference, the voltage reference circuit itself is then also powered down. The reference circuit is then powered back up for the next duty cycle sufficiently in advance of the reference consuming circuit such that any auto-zeroing and noise filtering operations required by the reference circuit are complete and a stable reference voltage is output at least simultaneously with, or slightly before, the reference consuming circuit begins to make use of the voltage reference signal. In this manner, synchronous duty-cycled operation of the voltage reference circuit with the reference-consuming circuit is obtained, with the consequence that power consumption by the reference circuit is reduced.

Abstract: Subject matter herein can include identifying a biochemical test strip assembly electrically, such as using the same test circuitry as can be used to perform an electrochemical measurement, without requiring use of optical techniques. The identification can include using information about a measured susceptance of an identification feature included as a portion of the test strip assembly. The identification can be used by test circuitry to select test parameters or calibration values, or to select an appropriate test protocol for the type of test strip coupled to the test circuitry. The identification can be used by the test circuitry to validate or reject a test strip assembly, such as to inhibit use of test strips that fail meet one or more specified criteria.

Abstract: An interface circuit to an electromagnetic flow sensor is described. In an example, it can provide a DC coupled signal path from the electromagnetic flow sensor to an analog-to-digital converter (ADC) circuit. Examples with differential and pseudo-differential signal paths are described. Examples providing DC offset or low frequency noise compensation or cancellation are described. High input impedance examples are described. Coil excitation circuits are described, such as can provide on-chip inductive isolation between signal inputs and signal outputs. A switched mode power supply can be used to actively manage a bias voltage of an H-Bridge, such as to boost the current provided by the H-Bridge to the sensor coil during select time periods, such as during phase shift time periods of the coil, which can help reduce or minimize transient noise during such time periods.

Abstract: Techniques for duplex communication and power transfer across an isolator are provided. In an example, a first transceiver coupled to a first side of an isolator can include a transmit modulator configured to receive first data and timing signals, to provide control signals to oscillate an output of the transceiver to transmit power and to order each half-cycle of an oscillation cycle of the output to transmit the first data. A second transceiver coupled to a second side of the isolator can include a receive detection circuit configured to compare a received oscillation cycle with a plurality of thresholds and to provide a plurality of comparator outputs indicative of reception of the positive half-cycle and the negative half-cycle, and a receive decoder configured to identify the order of half-cycles and to provide an output indicative of logic level of the first data.

Abstract: A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

Abstract: A power conversion apparatus or system can be configured to receive a high voltage alternating current (AC) signal at an input and to provide in dependence thereon a low voltage direct current (DC) signal from an output stage. The power conversion apparatus can include a main path comprising a high voltage capacitor in series with the input. In an example, the capacitor comprises a portion of an electric field energy harvesting system.

Abstract: Power systems having a DC content, such as photovoltaic (solar) panels present a problem if an arc fault appears because of a small break in a cable. The present disclosure describes an arc fault detection system that captures data in segments, examines the frequency spectrum to remove ‘false arc’ signatures and interference from a power converter of the power system, and then examines the cleaned frequency spectrum for arc events.

Abstract: A power factor correction device for providing tolerance to a fault condition in an input supply can include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit can interleave operation of the first boost circuit and operation of the second boost circuit such as to generate an output voltage when the input supply is received at the power factor correction device. The controller circuit can route, in response to the fault condition, a stored supply of the second boost circuit to an input of the first boost circuit. The controller circuit can control the first boost circuit to maintain the output voltage.

Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.

Abstract: Described are various current measurement techniques that can compensate for drift in shunt resistance. Determining a resistance of a shunt resistor, e.g., coupled to a battery terminal, can include introducing a known signal in sync with the chop phases of a dual system chop scheme, chopping the known signal out in the main signal path, and explicitly extracting the known signal in a parallel, additional signal deprocessing path.