Abstract: Described herein are electrochemical impedance spectroscopy (EIS) systems and methods that facilitate the allocation of a single stimulus generator across a number of electrolyzer stacks, each comprising a set of electrochemical cells. By distributing a stimulus signal, impedance data of the cells in each electrolyzer stack may be measured, e.g., to evaluate their condition or the condition of the stack without the need for separate stimulus blocks for each electrolyzer stack. In various embodiments, sharing the stimulus generator is enabled by sequentially directing stimulus signals to different stacks. The resulting response signals, indicative of the impedance of cells or entire stacks, are processed locally at each respective electrolyzer stack. Advantageously, the stimulus generator may be remotely located, e.g., at a location that is subject to less stringent safety measures, thereby lowering both equipment and operational expenses.

Abstract: A multi-phase regulator circuit includes one or more switching converter circuits. Each switching converter circuit includes a transformer including a primary winding and a multi-segment secondary winding, a primary side switch circuit configured to connect the primary winding to an input of the multi-phase regulator circuit, and multiple secondary side circuits including multiple coupled-inductor circuits. Each coupled-inductor circuit includes a first winding magnetically coupled to a second winding. Each segment of the transformer multi-segment secondary winding is operatively coupled to the first winding of a coupled-inductor circuit and each of the first windings is connected to an output of the multi-phase regulator circuit.

Abstract: Techniques, methods, circuits, and systems are provided for providing stabilization for a circuit. One example system includes a switching converter coupled to a power source; a low-pass filter coupled to a load device; a direct current (DC) path; and an alternating current (AC) path, where the DC path and the AC path are provided between the switching converter and the low-pass filter, and where the AC path provides a non-phased information signal to be used to compensate for a phase delay occurring in the DC path. In a more specific implementation, the DC path can be configured to provide control, at low frequency, for an output to the load device. In addition, an error amplifier can be to the DC path and the AC path, where the low-pass filter and the error amplifier can be configured to determine a switchover between the AC path and DC path.

Abstract: One embodiment is a method for counting charge events detected by a pixel in a photon-counting computed tomography (PCCT) scanning system comprising a plurality of discriminators, wherein each discriminator is associated with a respective one of a plurality of threshold voltage levels. The method includes detecting a signal output from one of the discriminators; incrementing a quantitative count corresponding to the threshold voltage level associated with the one of the discriminators if the detected discriminator output signal meets a first condition; and incrementing a qualitative count if the detected discriminator output signal meets at least one second condition.

Abstract: An integrated circuit including a multiplier-accumulator circuit pipeline including a plurality of MAC circuits. Each MAC circuit includes: (A) a multiplier circuit to multiply first input data and filter weight data to generate and output first product data having a floating point data format, and (B) a coarse floating point accumulator circuit including: (1) an alignment shift circuit to shift at least one field of the first product data and generate shifted first product data, and (2) fixed point addition circuitry, coupled to the alignment shift circuit, to add second input data and the shifted first product data using the fixed point addition circuitry. The plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline, in operation, each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.

Abstract: An integrated circuit comprising a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of MACs connected in series and (ii) a plurality of data paths including an accumulation data path, wherein each MAC includes a multiplier to multiply to generate product data and an accumulator to generate sum data. The integrated circuit further comprises a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with a MAC pipeline, wherein each control/configure circuit includes an accumulation data path which is configurable to directly connect to the accumulation data path of the MAC pipeline to form an accumulation ring when the control/configure circuit is configured in an accumulation mode, and an output data path configurable to directly connect to the output of the accumulation data path of the MAC pipeline when the control/configure circuit is configured in an output data mode.

Abstract: Several current sensing techniques are described that may be used to obtain an accurate current signal, which may help to achieve the best performance with a trans-inductor voltage regulator (TLVR) topology. The techniques may have the coupling effect from the secondary side included, so the current sensing signal is accurate for the regulation and other functions related to the current signal. The current sensing techniques may have more accurate gain and phase information in the middle frequency and high frequency ranges. The coupling effect from the secondary side may be well represented in the current sensing signal. The advantages of TLVR topology may be enhanced with accurate current information.

Abstract: Compact packages including microelectromechanical system (MEMS) devices and multiple application specific integrated circuits (ASICs) are described. These packages are sufficiently small to be applicable to contexts in which space requirements are particularly strict, such as in consumer electronics. These packages involve vertical die stacks. A first ASIC may be positioned on one side of the die stack and another ASIC may be positioned on the other side of the die stack. A die including a MEMS device (e.g., an accelerometer, gyroscope, switch, resonator, optical device) is positioned between the ASICs. Optionally, an interposer serving as cap substrate for the MEMS device is also positioned between the ASICs. In one example, a package of the types described herein has an extension of 2 mm×2 mm in the planar axes and less than 500-800 ?m in height.

Abstract: One or more electromagnetic radiation sources, such as a light emitting diode, may emit electromagnetic waves into a volume of space. When an object enters the volume of space, the electromagnetic waves may reflect off the object and strike one or more position sensitive detectors after passing through an imaging optical system such as glass, plastic lens, or a pinhole located at known distances from the sources. Mixed signal electronics may process detected signals at the position sensitive detectors to calculate position information as well as total reflected light intensity, which may be used in medical and other applications. A transparent barrier may separate the sources and detectors from the objects entering the volume of space and reflecting emitted waves. Methods and devices are provided.

Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.

Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

Abstract: A semiconductor-based stress sensor can include a bipolar transistor device with first and second collector terminals. An excitation circuit can provide an excitation signal to an emitter terminal of the bipolar transistor device, and a physical stress indicator for the semiconductor can be provided based on a relationship between signals measured at the collector terminals in response to the excitation signal. The signals can indicate a charge carrier mobility characteristic of the semiconductor, which can be used to provide an indication of physical stress. In an example, the physical stress indicator is based on a current deflection characteristic of a base region of the transistor device.

Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

Abstract: A soft-switching Phase-Shift Full-Bridge (PSFB) converter system may include a transformer comprising a primary side and a secondary side. Phase-leading circuitry and phase-lagging circuitry may be located on the primary side of the transformer. The phase leading a phase lagging circuitry may include one or more bridge switches. The system may further include clamping circuitry coupled to the secondary side of the transformer. The clamping circuitry configurable to, when in an active clamping mode, short the secondary side of the transformer. An inductance may be included on the primary side of the transformer to collect and store energy from an input source when the secondary side of the transformer is shorted. The energy stored in the inductance may be used to enable soft-switching of the bridge switches in the phase-lagging circuitry during a dead time or a circulating time of the bridge switches in the phase-leading circuitry.

Abstract: There is disclosed herein examples of systems and methods for compressing a signal. Samples of the signal can be segmented and the samples within each of the segments can be averaged to produce a value that can represent the samples within the segment. The number of samples to average in each segment may be determined based on an error threshold, such that the number of samples being averaged can be maximized to produce less data to be transmitted while maintaining the representation of the samples within the error threshold. In some embodiments, a signal can be separated into a timing reference, a representative periodic function, and a highly compressible error signal. The error signal can be utilized for reproducing a representation of the signal.

Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.

Abstract: The present subject matter relates to active balun circuits. An active balun circuit includes a plurality of transistors; an output transmission line connected to output terminals of the transistors; an input transmission line; and a plurality of serial capacitors coupled to an input terminal of the transistors and the input transmission line.

Abstract: A heat transfer element is disclosed. The heat transfer element can be configured to directly bond to a metal surface of an element. The heat transfer element can include a chamber that is defined at least in part by a housing that has a metal portion. The heat transfer element can also include a phase change material disposed in the chamber. The phase change material can be in thermal communication with the metal portion. The Heat transfer element can be bonded to the element to define a bonded structure.