Abstract: Methods are described for constructing a mechanical resonating structure by applying an active layer on a surface of a compensating structure. The compensating structure comprises one or more materials having an adaptive resistance to deform that reduces a variance in a resonating frequency of the mechanical resonating structure, wherein at least the active layer and the compensating structure form a mechanical resonating structure having a plurality of layers of materials A thickness of each of the plurality of layers of materials results in a plurality of thickness ratios therebetween.

Abstract: Various embodiments produce a semiconductor device, such a MEMS device, having metallized structures formed by replacing a semiconductor structure with a metal structure. Some embodiments expose a semiconductor structure to one or more a reacting gasses, such as gasses including tungsten or molybdenum.

Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.

Abstract: A sensor module can include a battery housing comprising a battery cavity sized and shaped to receive a battery. The battery cavity can be defined at least in part by a wall to be disposed about at least a portion of a periphery of the battery. A package housing can be disposed on the wall of the battery housing, the package housing smaller than the battery housing. An integrated device package can be disposed in or coupled with the package cavity. The integrated device package can include one or more integrated device dies. An interfacing feature can be coupled with the battery housing and extending transverse to the wall. The interfacing feature can be configured to transduce a biological signature into a signal to be processed by the integrated device package. An interconnect assembly can electrically connect the interfacing feature to the integrated device package.

Abstract: A scaled and configurable pre-processor array can allow minimal digital activity while maintaining hard real time performance. The pre-processor array is specially designed to process real-time sensor data. The interconnected processing units of the array can drastically reduce context swaps, memory accesses, main processor input/output accesses, and real time event management overhead.

Abstract: An integrated circuit may include a substrate and a dielectric layer formed over the substrate. A plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric elements may be disposed within the dielectric layer. The p-type thermoelectric elements and the n-type thermoelectric elements may be connected in series while alternating between the p-type and the n-type thermoelectric elements.

Abstract: A discrete-time (e.g., digital) filter can be used as an interpolation filter for processing an oversampled input signal, such as included as a portion of a sigma-delta digital-to-analog conversion circuit. An interpolation filter control circuit can be configured to adjust a filter order of the discrete-time interpolation filter at least in part in response to information indicative of an envelope signal magnitude. For example, higher-level input signals might be processed using an interpolation filter having a stop-band attenuation that is more stringently-specified (e.g., having greater attenuation) than a corresponding attenuation used for lower-level input signals. The filter order can be variable, such as varied in response to a detected envelope magnitude of the input signal to achieve power savings as compared to a filter having fixed parameters.

Abstract: Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage.

Abstract: Methods and devices for a remote control device for a display device are disclosed. In one embodiment, the remote control device may comprise a plurality of light sources that each has a light profile angled in a predetermined degree different from other light sources. In another embodiment, the remote control device may comprise a controller; and a plurality of optical detectors coupled to the controller. Each optical detector may generate a pair of electrical signals in response to incident light from a plurality of light sources located on a display device and the controller may calculate the position of the remote control device based on the electrical signals.

Abstract: Image capturing systems with interline CCD structures designed to reduce the delay between captures of subsequent image frames are disclosed. Proposed interline CCD structures include two or more sets of storage units associated with a given set of photodetecting elements, where each photodetecting element is associated with one storage unit of each set of storage units in that the charge generated by the photodetecting element during the acquisition of a particular image frame (i.e. during a particular exposure period) may be stored any one of these storage units prior to read-out. Providing multiple sets of storage units allows read-out of charge corresponding to one image frame and stored in one set of storage units while accumulating charge corresponding to another image frame in another set of storage units, thus reducing the delay between captures of different image frames. Consequently, errors and artifacts of the image capturing system can be minimized.

Abstract: Capacitive sensing can be used to measure electrostatic features of a space. Rudimentary capacitive sensing can be blurry. For instance, the resolution of a capacitive sensor generating a simple electric field is not very high, and the response to the simple electric field is also not very high. Using many capacitive sensors and special sets of excitation signals exciting the capacitive sensors, the capacitive sensors can generate specialized electrostatic fields. Because the specialized electrostatic fields provide different views of the space, enhanced inferences can be made from measurements of responses to those specialized electrostatic fields. Selecting certain specialized electrostatic fields can allow capacitive sensors to sense a focused region of the space. Repeating the steps with varied electrostatic fields can allow capacitive sensors to make enhanced inferences for many focused regions of the space, thereby increasing the resolution of capacitive sensing.

Abstract: The present disclosure relates generally to improving audio processing using an intelligent microphone and, more particularly, to techniques for processing audio received at a microphone with integrated analog-to-digital conversion, digital signal processing, acoustic source separation, and for further processing by a speech recognition system. Embodiments of the present disclosure include intelligent microphone systems designed to collect and process high-quality audio input efficiently. Systems and method for audio processing using an intelligent microphone include an integrated package with one or more microphones, analog-to-digital converters (ADCs), digital signal processors (DSPs), source separation modules, memory, and automatic speech recognition. Systems and methods are also provided for audio processing using an intelligent microphone that includes a microphone array and uses a preprogrammed audio beamformer calibrated to the included microphone array.

Abstract: Power line carriers (PLCs) are susceptible to transients and electromagnetic interference (EMI) on the power line. To address transients and EMI on the power line, an improved power PLC involves transmitting a signal over the power line using a controlled current source, where the current source is modulated by the signal. The current source output is designed to be independent of the voltage on the power line and the load, and thus, is less susceptible to transients and EMI on the power line. The system architecture of the improved PLC also allows for simple, predictable, and flexible termination. In an example implementation in the automotive industry, the improved high frequency PLC may provide a low cost replacement for existing communication interfaces. The improved PLC may consolidate system in-vehicle communication, reduce in-vehicle wiring, provide system flexibility, and decrease vehicle weight and system cost.

Abstract: The present disclosure describes a differential shield capacitive sensor design. The sensor design uses a differential measurement to measure capacitance and a pair of traces are used to differentially reject the response of the sensor traces and balance any parasitic capacitances. In some embodiments, the sensor design includes a differential sensor design on a bottom side of a flex circuit to differentially balance the environment and reject noise coupling to the sensor. The top side of the flex circuit can include a single ended design for proper environment sensing. The spatial arrangement and size of the sensors may vary depending on the application.

Abstract: Typically, complex systems require a separate and expensive equalizer at the output of an analog-to-digital converter (ADC). Rather than providing a separate equalizer, the effective Signal Transfer Function (STF) of a Multi-stAge noise SHaping (MASH) ADC can be modified by leveraging available digital filtering hardware necessary for quantization noise cancellation. The modification can involves adding calculations in the software previously provided for computing digital quantization noise cancellation filter coefficients, where the calculations are added to take into account equalization as well. As a result, the signal transfer function can be modified to meet ADC or system-level signal-chain specifications without additional equalization hardware. The method is especially attractive for high-speed applications where magnitude and phase responses are more challenging to meet.

Abstract: An exemplary energy harvester includes a piezoelectric diaphragm, an eccentric mass that rotates in response to external motion, and a piezoelectric stress inducer coupled with the eccentric mass and the piezoelectric diaphragm. The piezoelectric stress inducer deforms the piezoelectric diaphragm in response to rotational motion of the eccentric mass, causing the piezoelectric diaphragm to generate electrical energy.

Abstract: Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

Abstract: For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Abstract: An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

Abstract: An integrated device package is disclosed. The package includes a substrate comprising a cavity through a top surface of the substrate. A first integrated device die is positioned in the cavity. The first integrated device die includes one or more active components. A second integrated device die is attached to the top surface of the substrate and positioned over the cavity. The second integrated device die covers the cavity. Encapsulant can cover the second integrate device die.