Abstract: Apparatus and methods for switch-mode power supply start-up are provided herein. In certain embodiments, a switch-mode power supply includes an inductor and one or more power switches used to control a current through the inductor to provide voltage regulation. The switch-mode power supply uses external voltage levels to regulate one or more internal control signals (for example, for opening or closing the one or more power switches) to their zero output current switching state at the appropriate switch duty cycle. Furthermore, the switch-mode power supply can be implemented to provide a first pulse timing signal to establish the inductor current waveform for zero net output current delivery to a load.

Abstract: A system for adjusting a metastability error in an analog-to-digital converter (ADC) can include a first metastability test circuit, which can be configured to determine whether a comparator can be in a first stage of the ADC has settled to a determinate binary state at a first time. The system can also include a second metastability test circuit, which can be configured to determine whether the comparator in the first stage of the ADC has settled to the determinate binary state at a second time, where the first time can be a first specified time period before the second time. The system can also include correction circuitry, which can be configured to adjust an output of the first stage when one or more of the first metastability test circuit or the second metastability test circuit determines that the comparator in the first stage has not settled to the determinate binary state.

Abstract: A plethysmography (“PPG”) measurement system may include at least one source of PPG radiation and at least one auxiliary sensor for detection of PPG radiation. The radiation source emits a portion of the PPG radiation toward a subject and another portion along an optical path for direct communication between the PPG radiation source and the auxiliary sensor. The auxiliary sensor may develop a profile against which measurements from primary PPG sensors, which receive light returning from the subject, may be compared. From this comparison, new PPG signals may be generated that exhibit lower noise than the PPG signals output by PPG sensors. These noise mitigation techniques may be used advantageously by a PPG system to generate more accurate measurements and also to reduce power consumption by the radiation sources.

Abstract: It is not trivial to implement speech and natural language processing in offline embedded systems. Voice control of devices in various settings and applications can benefit from an embedded speech and natural language processing solution. One feature that helps to correct automatic speech recognition outputs is grammar projection. Another feature addresses situations where there is imperfect information or incomplete information by providing an application programming interface to enable structured queries and responses between an interpreter and an application.

Abstract: Disclosed herein are example systems and approaches for decomposition of composite signals. Decomposition of the composite signals may include derivation of two or more signals from the composite signals. An upper envelope and lower envelope may be determined for a composite signal in accordance with a smoothness parameter. A smooth estimate may be produced based on the upper envelope and the lower envelope, where the smooth estimate provides an estimate for a smooth component of the composite signal, which may be more accurate than legacy approaches.

Abstract: An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.

Abstract: Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).

Abstract: Techniques for automatic parameter tuning of active road noise cancellation systems are described herein. The system can automatically search for an optimal set of algorithm parameters based on recorded data. An active road noise cancellation algorithm and simulation can be embedded in an auto-differentiation framework, which allows gradients of the algorithm parameters to guide the automatic search and calculations of the algorithm parameters.

Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links, wherein the plurality of nodes are configured for full duplex, synchronized communication via a carrier-based modulation scheme over the bus links. A node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH) from the downstream node; measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information. The frames may include a header; a flexible payload defined by a stream mapping that assigns a byte location within the flexible payload to a stream; and a footer.

Abstract: An integrated distributed amplifier circuit can include an input transmission line structure comprising first unit cells including a first reactive circuit element and a first active circuit element, an output transmission line structure comprising second unit cells including a second reactive circuit element and a second active circuit element, and a termination circuit coupled to an end of the input transmission line structure. The termination circuit can include a current mirror circuit to establish a specified bias current for biasing respective first active circuit elements of the input transmission line structure. Such an approach can provide one or more of a broadband termination impedance and stable biasing conditions across different frequencies and power output levels.

Abstract: Various techniques are described for correcting distortion in an analog input signal after digitization in a receiver signal chain. The techniques include a system that stores concatenated distortion correction terms, allowing for efficient data handling and processing. The techniques further include a system that has a smaller number of replica memories compared to primary memories, which store operational data. The replica memories are updated with new data and may be swapped with primary memories to update them without interrupting system operations. The techniques further include a dither system that uses two memories to store and process the dithered signals, which are then combined to produce a noise-corrected digital output. The techniques further include a system to correct distortions in analog input signals processed through multiple parallel paths.

Abstract: Apparatus and methods for programming multiple parameters per pin of an IC are disclosed herein. In certain embodiments, system operation parameters of an IC are set using external component(s) in conjunction with an internal detection circuit of the IC. The internal detection circuit allows for programming of multiple parameters with one pin of the IC, thereby reducing package size, board area, and/or chip complexity. For example, the teachings herein allow for detection of three or more unique parameters or states per pin, significantly reducing the part pin count and board area.

Abstract: In some examples of both networks and methods, a data communication network includes a plurality of nodes. The nodes include a main node (MN) and at least one sub node (SNi=SN0, . . . SNX). Each node includes a node transceiver. The node transceiver is operable to perform data communication in accordance with a first network protocol for power over data via a pair of conductors (e.g., the conductors of bus). A physical layer includes a cable segment (e.g., the cable segment of bus) between each node. Each cable segment includes a plurality of pairs of conductors (e.g., pairs) and a connector (e.g., 8P8C connector—though other connectors with multiple pairs of conductors can be used) at each end. A first pair of the conductors (e.g., connected to pin 4 and pin 5 of the 8P8C connector) implements the first network protocol between the nodes. One or more of the remaining pairs of the conductors provide supplemental power to the nodes 102.

Abstract: Described herein are software programmable isolated devices. The isolated device may be programmable in that some of the characteristics of the isolated device may be set based upon input provided by a user. The isolated device may allow the user to program the activation or deactivation of each channel independently of the activation and deactivation of the other channels. Additionally, or alternatively, the isolated device may allow the user to program the direction of transmission of each channel independently of the direction of transmission of the other channels. Additionally, or alternatively, the isolated device may allow a user to program the data rate at which each channel communicates independently of the data rates of the other channels. Additionally, or alternatively, the isolated device may allow a user to program the delay associated with each channel independently of the delays associated with the other channels.

Abstract: Packaging of microfabricated devices, such as integrated circuits, microelectromechanical systems (MEMS), or sensor devices is described. The packaging is 3D heterogeneous packaging in at least some embodiments. The 3D heterogeneous packaging includes an interposer. The interposer includes stress relief platforms. Thus, stresses originating in the packaging do not propagate to the packaged device. A stress isolation platform is an example of a stress relief feature. A stress isolation platform includes a portion of an interposer coupled to the remainder of the interposer via stress isolation suspensions. Stress isolation suspensions can be formed by etching trenches through the interposer.

Abstract: Fault monitoring systems and methods presented herein perform steps comprising, in response to a host device receiving a valid command, if no fault condition is present in a circuit, communicating an acknowledgement response to the host device. Whether a fault condition is present in the circuit may be determined by a monitoring circuit. If a fault condition is found, an error acknowledgement response that is different from the acknowledgement response may be communicated to the host. Contrariwise, if an invalid command is received from the host, no acknowledgement response and no error acknowledgement response are communicated to reduce unnecessary communication.

Abstract: One embodiment is a baseline restoration (“BLR”) circuit for a photo-counting computed tomography (“PCCT”) signal chain, the BLR circuit comprising a comparator for comparing a shaper voltage output from a shaper component of the PCCT signal chain with a baseline voltage, the comparator outputting a single bit indicative of whether the shaper voltage is above or below the baseline voltage; a low pass filter connected to filter a voltage signal output from the comparator; and a transconductor connected to receive a filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed the current signal back to an input of the PCCT signal chain.

Abstract: Aspects of the present disclosure include isolating a target scene object from multiple images of a time-of-flight (TOF) sensor. Multiple images from a TOF sensor can be transformed into multiple three-dimensional (3D) point clouds. In each of the multiple 3D point clouds, one or more large planes having a minimal threshold size can be identified. A common 3D point cloud can be generated by aligning rotated and translated point clouds corresponding to at least a portion of the multiple 3D point clouds. The common 3D point cloud can be rotated and translated to have one of one or more large planes identified as a ground plane within a common coordinate system of the common 3D point cloud, and a target object can be isolated.

Abstract: A gyroscope includes a substrate, a proof mass coupled to the substrate and configured to move in direction of an X axis and in direction of a Y axis orthogonal to the first axis, an X axis shuttle to selectively drive the proof mass along the X axis as a drive axis or sense movement of the proof mass along the X axis as a sense axis in response to the proof mass driven along the Y axis as the drive axis, and a Y axis shuttle to selectively sense movement of the proof mass along the Y axis as a sense axis in response to the proof mass driven along the X axis or drive the proof mass along the Y axis as the drive axis. The X axis shuttle is symmetric to the Y axis shuttle along a diagonal axis that is diagonal to both the X axis and the Y axis. The X and Y axis shuttles have gaps designed for a predetermined DC voltage to generate spring softening (negative cubic nonlinearity) that is equal to spring hardening (positive cubic nonlinearity), ensuring linear motion at high amplitudes (? of the capacitive gap).

Abstract: Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.