Patents Assigned to Analog Devices, Inc.
  • Publication number: 20240089153
    Abstract: Digital isolators operable in multiple power modes are described. The digital isolators include a low power mode, in which some circuitry of the isolator operates in a lower power state than in other mode(s) of operation or may be deactivated, and in which data communication across the isolator is not permitted. The isolator may wake from the low power mode in response to a detected event or may periodically wake. Circuitry on one side of the isolator may dictate when and how the isolator wakes from a lower power mode.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: Analog Devices, Inc.
    Inventors: Jason J. Ziomek, Eric C. Gaalaas
  • Patent number: 11907160
    Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 20, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
  • Patent number: 11899480
    Abstract: A voltage regulator circuit can include two feedback loops, such as to reduce or suppress an unwanted transient condition in an output voltage during transient conditions such as during startup or during load current demand transients. One of the two feedback loops can include a shunt device arranged to provide a temporary current pathway during the transient condition to change current provided to a load connected to an output of the voltage regulation circuit. In addition, or instead, the voltage regulator circuit can include an open-loop regulation circuit separate from a loop corresponding to the first error amplifier. The open-loop regulator circuit can operate in a lower-power mode as compared to a closed-loop regulator circuit. A portion or an entirety of the voltage regulator circuit can be implemented in an integrated circuit, such as monolithically.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Colin Tse, James Lin
  • Patent number: 11895588
    Abstract: Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: February 6, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Brett Warneke, Gary Wayne Ng, Mark Alan Lemkin
  • Patent number: 11894322
    Abstract: Radio frequency integrated device packages having bump and/or ball launch structures are disclosed herein. The bump launch structures can comprise patterned metallic and insulating material that substantially matches the impedance of a radio frequency integrated device die. The ball launch structures can comprise patterned metallic and insulating material that substantially matches the impedance of a system board.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 6, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Bruce E. Wilcox
  • Patent number: 11892467
    Abstract: A microelectromechanical systems (MEMS) accelerometer is provided, comprising a substrate disposed in a plane defined by a first axis and a second axis perpendicular to the first axis; a first proof mass and a second proof mass coupled to the substrate and configured to translate in opposite directions of each other along a third axis perpendicular to the first and second axes; and at least one lever coupling the first proof mass to the second proof mass, wherein, the MEMS accelerometer is configured to detect acceleration along the third axis via detection of translation of the first and second proof masses along the third axis; and the MEMS accelerometer exhibits symmetry about the first and second axes.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: February 6, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Kemiao Jia, Xin Zhang, Michael Judy
  • Publication number: 20240039547
    Abstract: Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: Analog Devices, Inc.
    Inventor: Khiem Quang NGUYEN
  • Publication number: 20240037211
    Abstract: Systems, devices, and methods related to wireless battery management system (wBMS) are provided. For example, a wBMS network manager comprises a memory to store a list of hardware identifiers (IDs), wherein each hardware ID in the list is associated with a respective one of a plurality of battery modules; and mapped, based on a predetermined mapping, to a different one of a plurality of source IDs; an interface to receive, from a remote battery module, a packet including a source ID and a hardware ID associated with the remote battery module; and one or more processing units to search, using the source ID in the received packet and the predetermined mapping, for a first hardware ID from the list of hardware IDs; and authenticating the remote battery module based on a comparison of the hardware ID in the received packet to the first hardware ID from the list.
    Type: Application
    Filed: November 29, 2022
    Publication date: February 1, 2024
    Applicant: Analog Devices, Inc.
    Inventor: Douglas Dealton LEWIS
  • Patent number: 11874791
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 16, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Martin Kessler, Miguel A. Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
  • Patent number: 11876346
    Abstract: A laser pulse emitter circuit comprises a laser diode and a laser diode driver circuit. The laser diode driver circuit includes an inductive circuit element in series with the laser diode, at least one capacitive circuit element connected in series with the inductive circuit element, and a switch circuit configured to activate the laser diode using duty cycling that includes an on-period and an off-period, wherein energy used in an activation of the laser diode is stored in the inductive circuit element and the at least one capacitive circuit element, and the stored energy is recycled by use in a subsequent activation of the laser diode.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: January 16, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Junhua Shen
  • Patent number: 11864886
    Abstract: Herein disclosed is a system that may be implemented within a headphone to facilitate hearing testing. Implementation of the system in the headphone may include implementation of tone generation circuitry and sound pressure level measurement circuitry being implemented in the headphone limiting the amount of calibration for accurate measurement when performing a hearing test.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 9, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Mikael Mortensen
  • Patent number: 11870554
    Abstract: A network node device of an area network includes physical layer (PHY) circuitry configured to transmit and receive frames of data via a communication link of the communication network; medium access layer (MAC) circuitry; a receive interface between the PHY circuitry and the MAC circuitry, and timestamp circuitry. The receive interface includes a receive clock signal and a DLL. The timestamp circuitry is configured to produce multiple sample signals derived from the receive clock signal using the DLL and a local clock signal of the network node, and produce a timestamp offset using the multiple sample signals. The timestamp offset is representative of an instantaneous phase offset between a local clock of the network node and a local clock of a neighbor node of the network node.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: January 9, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Andrew David Alsup
  • Patent number: 11870456
    Abstract: Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: January 9, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Jesper Steensgaard-Madsen
  • Patent number: 11862864
    Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: January 2, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Hsin-Chang Lin
  • Patent number: 11863138
    Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: January 2, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Devrim Aksin
  • Patent number: 11863165
    Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 2, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Lawrence A. Singer
  • Patent number: 11848610
    Abstract: A switching converter circuit comprises a converting circuit stage, an error amplifier, and a control circuit. The converting circuit stage includes a magnetic circuit element and a switching circuit configured to convert an input voltage to a regulated output voltage by charging and discharging the magnetic circuit element using activation pulses generated using a system clock signal. The error amplifier generates a control voltage using the output voltage. The control circuit varies time between successive activation pulses according to the control voltage, and the successive activation pulses are synchronized to the system clock signal.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: December 19, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Hua Chen
  • Patent number: 11837403
    Abstract: Systems and methods involving nanomaterial-based electrodes, such as supercapacitor and battery electrodes that can be flexible, are described.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 5, 2023
    Assignees: Massachusetts Institute of Technology, Analog Devices, Inc.
    Inventors: Karen K. Gleason, Brian L. Wardle, Estelle Cohen, Yue Zhou, Xiaoxue Wang, Yosef Stein
  • Patent number: 11830289
    Abstract: Far field devices typically rely on audio only for enabling user interaction and involve only audio processing. Adding a vision-based modality can greatly improve the user interface of far field devices to make them more natural to the user. For instance, users can look at the device to interact with it rather than having to repeatedly utter a wakeword. Vision can also be used to assist audio processing, such as to improve the beamformer. For instance, vision can be used for direction of arrival estimation. Combining vision and audio can greatly enhance the user interface and performance of far field devices.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 28, 2023
    Assignee: ANALOG DEVICES, INC.
    Inventors: Atulya Yellepeddi, Kaushal Sanghai, John Robert McCarty, Brian C. Donnelly, Nicolas Le Dortz, Johannes Traa
  • Patent number: 11829864
    Abstract: An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: November 28, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Sung Ung Kwak, Robert Michael Muchsel