Abstract: A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

Abstract: A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.

Abstract: A test socket for a surface mount IC chip includes an array of double-ended spring contacts that extend out from opposite sides of a substrate, with a positioning frame on top of the substrate for aligning a chip and its leads with the upper contact heads. The spring contacts preferably have hollow elongate bodies with contact heads extending out from opposite sides under an internal spring bias. The socket can be formed from two laminates which have a series of aligned openings for the spring contacts, with expanded midsections on the spring contacts press-fit into the laminate openings and thereby securing holding the laminates together. A standoff on the upper socket surface vertically positions the IC chip, and provides the proper contact pressure between its leads and the spring contacts. The test socket can be removably mounted to a PC test board, with a releasable clamping device such as an air cylinder used to hold a chip to be tested in place within the socket.

Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator.

Abstract: A detector cell for a logarithmic includes a differential pair of inputs across which a input signal V.sub.0 is applied across. The detector cell also includes a pair of differential outputs. The detector cell is comprised of three transistors Q4, Q5 and Q6. Resistors are coupled between the bases of adjacent transistors. The resistors form a voltage divided across which the input signal V.sub.0 is divided. The emitters of the three transistors are coupled to a current source, which sends a predetermined amount of current Ihd D. The collectors of the first and third transistors are coupled together to form a first differential input of the differential input pair. The collector of the second transistor alone forms the second differential input of the pair. The emitter area of the second transistor is ratioed with respect to the first and third so that a current I.sub.1 flowing through the first differential output is equal to a current I.sub.

Abstract: A programmable gain amplifier including first and second gain elements are connected by an impedance selector which allows programmability of the gain of both gain elements. The impedance selector is connected in series with the output of the first gain element. The impedance selector places an impedance in the feedback path of the first gain element or the input path of the second gain element. Errors introduced in the signal path due to the switches are attenuated by the open loop gain of the first gain element. The gain may be equally divided between both stages of the amplifier to allow for optimum band width. Optimum noise performance may be obtained by placing most of the gain in the first stage. An instrumentation amplifier may also be made which further includes a third gain element connected to the gain element with a second impedance selector in a manner similar to the connection of the first gain element to the second gain element.

Abstract: A package for housing integrated circuit chips that provides EMF shielding and thermal protection, while conforming to an industry recognized package outline, is provided. This EMF shielding and thermal protection is achieved by providing an electrically conductive heat sink that provides heat dissipation and that, together with a separate electrically conductive layer, also acts as an EMF shield. The heat sink contains a recess and is positioned against the conductive layer with the recess facing the conductive layer. The integrated circuit (IC) resides inside the cavity formed by the heat sink and conductive layer and is protected from EMF by the heat sink and conductive layer. The heat sink, electrically conductive layer and IC are then encapsulated in an electrically insulating molding compound that is molded to an industry recognized package outline. Additional ICs can be housed in this package by attaching them to the side of the electrically conductive layer opposite the heat sink.

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator.

Abstract: A self-aligned capacitor structure and method of making it includes an insulating support substrate with the capacitor disposed on the insulating substrate with a first conducting extending across the capacitor in the first dimension. The capacitor includes a first electrode interconnected with the first conductor, a second electrode supported by the substrate and interconnected with the second conductor, and a dielectric medium between the first and second electrodes. The first and second electrodes being coterminous in both directions in the first dimension for eliminating parasitic capacitance between the first conductor and the second electrode.

Abstract: An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.

Abstract: An integrated circuit metal-oxide-metal capacitor and method of making it which involves a support layer; a first conductive electrode on the support layer; a dielectric film on the first conductive electrode; a second conductive electrode disposed on the dielectric film and formed from the first level metallization interconnect layer of the integrated circuit; an interlevel dielectric layer; a first contact via extending through the interlevel dielectric layer and the dielectric film to the first conductive electrode; a second contact via extending through the interlevel dielectric layer to the second conductive electrode; and first and second terminals formed from the second level metallization interconnect layer of the integrated circuit contacting the first and second vias, respectively.

Abstract: An SOI/DI IC chip including a handle wafer in the form of a section of silicon substrate contiguous with the layer of insulation beneath the silicon slice containing the device regions separated by trenches filled with low-conductivity polysilicon dielectric. One of the trenches is etched through the layer of insulation, and the polysilicon in that trench is doped to provide desired electrical conductivity to establish electrical contact with the handle wafer. Metallization is applied over the top of this one trench to make possible electrical connection to the handle wafer from above the chip by use of conventional wiring techniques.

Abstract: A switched-capacitor auto-zero integrator includes and integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an Input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge of the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval: and a correction sub-interval.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes two input terminals for sequentially receiving a plurality of input signal AC voltage bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminals, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. The demodulation circuitry includes translation circuitry, coupled to the input, for sequentially translating each input voltage burst to a translated current. A rectifier circuit, coupled to the translation circuitry, including an absolute value circuit and a current mirror circuit, sequentially rectifies each translated current and produces a driving signal. An integrator, coupled to the rectifier circuit, sequentially integrates each driving signal. The integrator includes an integration capacitor which is sequentially charged by each driving signal.

Abstract: A CMOS input circuit that has a first inverter stage for comparing non rail-to-rail digital input voltages to a threshold voltage, and producing inverted CMOS output voltages is disclosed. The inverted output voltages are approximately equal to a low CMOS supply voltage plus an offset voltage and a high CMOS supply voltage. The inverter includes PMOS and NMOS transistors that are connected to receive a common input voltage at their gates and to have a common drain current. The PMOS' source is connected to the high supply voltage, and the NMOS' source is connected through a voltage drop circuit element to the low supply voltage. The inverted output voltage is produced at the connection of the PMOS and NMOS transistors' drains. The NMOS and PMOS transistors have gate width and length parameters W.sub.N, L.sub.N and W.sub.P, L.sub.P, respectively. The ratio ##EQU1## is selected so that the threshold voltage is set between the maximum low and minimum high input signals for a desired range of high supply voltages.

Abstract: An accelerometer comprising a microfabricated acceleration sensor and monolithically fabricated signal conditioning circuitry. The sensor comprises a differential capacitor arrangement formed by a pair of capacitors. Each capacitor has two electrodes, one of which it shares electrically in common with the other capacitor. One of the electrodes (e.g., the common electrode) is movable and one of the electrodes is stationary in response to applied acceleration. The electrodes are all formed of polysilicon members suspended above a silicon substrate. Each of the capacitors is formed of a plurality of pairs of electrode segments electrically connected in parallel and, in the case of the movable electrodes, mechanically connected to move in unison. When the substrate is accelerated, the movable electrodes move such that the capacitance of one of the capacitors increases, while that of the other capacitor decreases.

Abstract: A voltage regulator is capable of providing multiple fixed outputs plus a user-selected output by the use of a window comparator circuit that produces one of three different possible outputs, depending upon whether an input control signal is above, below or within the window voltage range. Two of the outputs operate different switches within a feedback circuit for a multiplying operational amplifier, causing the amplifier to produce different regulated output levels depending upon which switch is operated. The third window output disables the operational amplifier and establishes a mode in which the regulated output is set by an external feedback circuit for another operational amplifier, with the external circuit connected across the circuit's input and output terminals.