Abstract: A substantially planar waveguide for dynamically controlling the out-of-plane angle at which a light beam exits the waveguide. Generally, liquid crystal materials may be disposed within a waveguide in a cladding proximate or adjacent to a core layer of the waveguide. In one example, the waveguide may contain one or more taper regions such that the light beam exits the waveguide and propagates out-of-the-plane of the waveguide into an out-coupling medium at a propagation angle. In one example, the waveguide may contain one or more electrodes onto which one or more voltages may be applied. The magnitude of the propagation angle may be electronically controlled by altered by controlling or altering the magnitude of the one or more applied voltages.

Abstract: A crosspoint switch matrix may include a plurality of point cells provided at intersections between a plurality of input pathways and a plurality of output pathways. The input pathways may be partitioned into groups, each group defined by a demultiplexer that forwards an input signal to the point cells within the group and/or to a demultiplexer of a succeeding group. The output pathways may be partitioned into groups, each group defined by a multiplexer that forwards a signal from an active point cell to an output of the matrix. Multiplexers of groups in intermediate positions between the point cell and the matrix output may relay the output signal between the multiplexers along a bypass pass. When both the input pathways and output pathways are so partitioned, each point cell may be a member of one input pathway group and one output pathway group.

Abstract: Thick (i.e., greater than two microns), fine-grained, low-stress tungsten MEMS structures are fabricated at low temperatures, particularly for so-called “MEMS last” fabrication processes (e.g., when MEMS structures are fabricated after electronic circuitry is fabricated). Means for very accurately etching structural details from the deposited tungsten layer and for strongly and stably anchoring the tungsten layer to an underlying substrate are disclosed. Also, means for removing a sacrificial layer underlying the mobile tungsten layer without damaging the tungsten or allowing it to be drawn down and stuck by surface tension is disclosed.

Abstract: An analog-to-digital converter (ADC) circuit including error correction circuitry for correcting offset drifts in an ADC, such as a successive approximation register (SAR) ADC. The offset drifts can be reduced, such as by sampling the offset following an analog-to-digital conversion and subsequently providing an error correction signal based on the sampled offset.

Abstract: A substantially planar waveguide for dynamically controlling the out-of-plane angle at which a light beam exits the waveguide. Generally, liquid crystal materials may be disposed within a waveguide in a cladding proximate or adjacent to a core layer of the waveguide. In one example, the waveguide may contain one or more taper regions such that the light beam exits the waveguide and propagates out-of-the-plane of the waveguide into an out-coupling medium at a propagation angle. In one example, the waveguide may contain one or more electrodes onto which one or more voltages may be applied. The magnitude of the propagation angle may be electronically controlled by altered by controlling or altering the magnitude of the one or more applied voltages.

Abstract: A soft start-up method is provided comprising: producing an initialization signal on a primary winding side of a transformer; using a comparison of the initialization signal with a signal having a value indicative of a current in the primary winding to control a switch operatively disposed between a voltage source and the primary side; transmitting the initialization signal over a galvanically isolating communication medium from the primary side to a secondary winding side of a transformer; at the secondary winding side, comparing a reference voltage signal with a secondary winding output voltage signal; in response to a match between the reference signal and the secondary winding output voltage signal, transmitting a comparison voltage signal over the galvanically isolating communication medium from the secondary side to the primary side; at the primary side, comparing the initialization signal with the transmitted comparison voltage signal; and in response to a match between the initialization signal the an

Abstract: A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.

Abstract: Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Abstract: A self-biased cascode current mirror/scaler circuit can include a bias FET biased with an input current to generate a gate-source voltage, which can be divided by a bias circuit into a first voltage component (e.g., at a threshold voltage) and a second voltage component (at a FET drain-source saturation voltage or edge of saturation voltage). An input FET of the current mirror/scaler circuit can receive approximately the input current or a function thereof. A gate of the input FET can be biased at the first voltage component in sum with a FET drain-source saturation voltage or edge of saturation voltage of the input FET. A gate of the output FET can be connected to the gate of the input FET. A gate of a cascode FET in series with the output FET can be biased at the first voltage component in sum with the second voltage component in sum with the FET drain-source saturation voltage or edge of saturation voltage of the input FET.

Abstract: Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a substrate, a wall attached to the substrate, a first adhesive layer disposed between a bottom surface of the wall and a top surface of the substrate, and a second adhesive layer disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer different from the first adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground.

Abstract: Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

Abstract: A method compensates for a sensitivity of an inertial sensor having a resonator and an accelerometer. The method includes adding a test signal to a quadrature tuning voltage applied to the resonator of the inertial sensor. The method also includes receiving a quadrature error signal from the accelerometer of the inertial sensor. The method also includes detecting a phase difference between the quadrature error signal and the test signal. The method also includes determining a bandwidth of the accelerometer based on the detected phase difference, the bandwidth indicating the sensitivity of the accelerometer.

Abstract: According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.

Abstract: Activity monitors and smart watches utilizing optical measurements are becoming widely popular, and users expect to get an increasingly accurate estimate of their heart rate (HR) from these devices. These devices are equipped with a light source and an optical sensor which enable estimation of HR using a technique called photoplethysmography (PPG). One of the main challenges of HR estimation using PPG is the coupling of motion into the optical PPG signal when the user is moving randomly or exercising. The present disclosure describes a computationally feasible and fast HR estimation algorithm to be executed at instances of little or no motion. Resulting HR readings may be useful on their own, or be provided to systems that monitor HR continuously to prevent the problem of such systems being locked on an incorrect HR for long periods of time. Implementing techniques described herein leads to more accurate HR measurements.

Abstract: An analog to digital converter (ADC) system includes two signal paths in parallel with each other, where the signal paths include separate ADC circuits to separately operate on a same input signal and output separate digital signals. A difference signal is calculated as a difference of the digital signals output from the two signal paths to determine an error present in one or both of the signal paths. The error may be modulated in one or both of the signal paths and demodulated from the difference signal according to a same digital modulation pattern to compute an error compensation signal to compensate for at least one of the modulated error and a secondary error resulting from the modulation of the error.

Abstract: A wideband RF tuner with blocker signal detector for detection of blocking signals and for fast recovery from noise limited region.

Abstract: A capacitive microelectromechanical systems (MEMS) sensor is provided, having conductive coatings on opposing surfaces of capacitive structures. The capacitive structures may be formed of silicon, and the conductive coating is formed of tungsten in some embodiments. The structure is formed in some embodiments by first releasing the silicon structures and then selectively coating them in the conductive material. In some embodiments, the coating may result in encapsulating the capacitive structures.

Abstract: Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.

Abstract: Disclosed herein are microphone arrays for directional reception, along with related system, devices, and techniques. For example, a four-microphone array for directional signal reception may include first, second, and third microphones arranged such that projections of the first, second, and third microphones in a plane provide corners of a triangle in the plane. In some embodiments, a fourth microphone may be arranged such that a projection of the fourth microphone in the plane is disposed in an interior of the triangle. In other embodiments, the fourth microphone may be arranged such that the projection of the fourth microphone in the plane is disposed outside the interior of the triangle, and a distance between the first microphone and the second microphone is different from a distance between the first microphone and the third microphone.

Abstract: A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers.