Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.

Abstract: A system for digitizing the magnitude of a first parameter, which can be inferred by applying to a second parameter and digitizing the magnitude of a resulting third parameter. The circuit which applies the second parameter has an associated bias point with which the magnitude of the second parameter varies. The value of the first parameter can result in an error in the value of the second parameter which results in an error being incurred when the digitized value of the third magnitude is used to infer a digitized value of the magnitude of the first parameter. This is avoided by adjusting the bias point with each successive trial and employing a sequential-trial ADC which performs sequential comparisons between the third magnitude and respective decision thresholds, such that there is no error in the magnitude of the second parameter when the third magnitude is equal to the decision threshold for a particular trial.

Abstract: Previously available analog domain decimation techniques are limited to simple equally-weighted averaging of photosite outputs. Decimation of a Bayer pattern image by an even-factor, such as by two or six, using simple equally-weighted averaging of photosite outputs in the analog domain results in effective sampling locations that are unevenly spaced apart. Standard interpolation of the unevenly spaced effective sampling locations generates image artifacts that reduce the quality of the reconstructed image in the smaller format because standard interpolation methods assume that the effective sampling locations are evenly spaced. Implementations of systems, methods and apparatus disclosed herein aim to produce substantially evenly spaced effective sampling locations in the analog domain.

Abstract: Inertial sensors with reduced sensitivity to quadrature errors and micromachining inaccuracies include a gyroscope incorporating two specially-configured single-axis gyroscopes for sensing rotations about two orthogonal axes (the axes of sensitivity) in the device plane, where each single-axis gyroscope includes a resonator having two rotationally-dithered shuttles interconnected by a fork and each shuttle is configured to tilt out-of-plane along a tilt axis perpendicular to the axis of sensitivity and includes corresponding Coriolis sensing electrodes positioned along an axis perpendicular to the tilt axis (i.e., parallel to the axis of sensitivity). The two single-axis gyroscopes may be interconnected, e.g., by one or more in-phase or anti-phase couplings interconnecting the forks and/or the shuttles.

Abstract: A microphone system has a primary microphone for producing a primary signal, a secondary microphone for producing a secondary signal, and a selector operatively coupled with both the primary microphone and the secondary microphone. The system also has an output for delivering an output audible signal principally produced by one of the to microphones. The selector selectively permits either 1) at least a portion of the primary signal and/or 2) at least a portion of the secondary signal to be forwarded to the output as a function of the noise in the primary signal.

Abstract: A voltage regulator comprises first and second bipolar transistors operating at different current densities; a resistor is connected between their bases across which ?VBE appears. A third bipolar transistor is connected such that the voltages at the bases of the first and third transistors are equal or differ by a PTAT amount. A current mirror is arranged to balance the collector current of one of the second and third transistors with an image of the collector current of the first transistor when the output node is at a unique operating point. The operating point includes both PTAT and CTAT components, the ratio of which can be established such that the operating point has a desired temperature characteristic. A transistor connected to the output node and driven by the output of the current mirror regulates the output voltage by negative feedback.

Abstract: A microchip system has a package forming a hermetically sealed interior, and MEMS structure within the interior. The system also has a gas sensor for detecting the concentration of at least one of oxygen or hydrogen within the interior.

Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.

Abstract: Apparatus and methods are disclosed, such as those involving an electronic device. One such apparatus includes a transmitter; a receiver; and a transmit/receive switch configured to electrically block the receiver from the transmitter during a transmit period. The transmit/receive switch includes one or more MOSFETs coupled between an input node and an output node, the input node being electrically coupled to the transmitter, the output node being electrically coupled to the receiver. The one or more MOSFETs are configured to be off during the transmit period. The transmit/receive switch further includes a clamp circuit configured to couple the output node to ground during the transmit period. This configuration effectively protects the receiver while minimizing switching artifacts.

Abstract: A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system.

Abstract: A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.

Abstract: A voltage boost circuit is driven with a clock signal CLK which toggles between voltages V1 and V2. A first MOSFET is coupled between CLK and an output node OUT, and at least one additional MOSFET is coupled between OUT and a supply voltage. The first terminal of a capacitance is coupled at its first terminal to OUT, and at its second terminal to a delay circuit arranged to toggle its output to ˜V2 or ˜V1 a predetermined amount of time after the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2 or ˜V1, respectively. The capacitance is charged to ˜V2 when the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2, and OUT is increased to a voltage greater than V2 when the output of the delay circuit toggles to ˜V2. The only active device junctions subjected to the boosted voltage are MOSFET well-substrate junctions, such that no active devices are overstressed.

Abstract: Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.

Abstract: Efficiently controlled converter system embodiments are provided to operate in different operational modes. In a first operational PWM mode, first and second transistors are switched with a feedback-controlled duty cycle to thereby realize an inductor current that maintains a system output voltage. In a second operational PFM mode, after the output voltage decays to a lower threshold over a decay time, the control and synchronous transistors are driven a sufficient number of times to raise the output voltage to an upper threshold. The systems are controlled to efficiently transition between the first and second operational modes. For example, a converter system preferably transitions to the second PFM operational mode when current peaks of the inductor current drop below a predetermined current threshold and the system preferably transitions to the first PWM operational mode when the output voltage drops to a predetermined reference voltage.

Abstract: An inertial sensor includes driving piezoelectric transducers for enabling an oscillation of a resonator, sensing piezoelectric transducers for enabling a detection of a movement of the inertial sensor, and piezoelectric compensating elements substantially equidistantly among the driving and the sensing piezoelectric transducers, wherein the compensating elements and the resonator form corresponding capacitors having capacitive gaps, and wherein, during the oscillation of the resonator, changes in electrostatic charges stored in the capacitors are measured with the compensating elements and are modified so as to modify the oscillation of the resonator.

Abstract: A current limit scheme for current-mode DC-DC converters. The current limit scheme is used to limit the current through the inductor during a current limit event. Current flows through the inductor alternately from first and second power devices, with one of said devices operating in the on-state while the other is in the off-state. The current through the second power device is sensed and tracked if the peak inductor current exceeds a particular value. The inductor current is regulated by modulating the on-time of the first power device that delivers current from the input voltage source to the output through the inductor. Thus, the modulator adjusts the on-time of the first power device using past and present information related to the current flowing through the second power device and the instantaneous output voltage of the converter to limit the peak inductor current from exceeding a maximum value.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit.

Abstract: Timing generators and methods of generating timing signals are disclosed. In one implementation, a timing generator for an imaging device includes a timing generator memory configured to store timing information, a timing core coupled to the timing generator memory and configured to read the timing information from the timing generator memory, and a processor core coupled to the timing core and configured to control a plurality of counters. The timing core can be further configured to generate a plurality of timing patterns based on the timing information and the plurality of counters. The timing generator can also be configured to generate a plurality of toggle positions for a plurality of timing signals based on the plurality of timing patterns.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.