Abstract: A receiver for a light detection and range finding system is disclosed. The receiver can include an optoelectrical device to receive a pulse of light reflected from a target and to convert the pulse of light to a current pulse. The receiver can also include a transimpedance amplifier (TIA) to convert the current pulse to a voltage pulse. The receiver can also include a tunable filter that has an input coupled to an output of the TIA. The tunable filter can have a frequency response that is adjustable. The TIA and the tunable filter can be disposed on a single integrated circuit (IC) die.

Abstract: A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0 V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.

Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Abstract: Digital to analog converter generates an analog output corresponding to a digital input by controlling DAC cells using bits of the digital input. The DAC cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the DAC cells may have duty cycle error or mismatches. To compensate for the duty cycle error of a DAC cell, a small amount of charge is injected into a low-impedance node of a DAC cell when the data signal driving the DAC cell transitions, or changes state. The small amount of charge is generated using a capacitive T-network, and the polarity of the charge injected is opposite of the error charge caused by duty cycle error. The opposite amount of charge thus compensates or cancels out the duty cycle error, and duty cycle error present at the output of the DAC cell is reduced.

Abstract: Techniques are described for calibrating sensors for use in systems in the presence of offset. Sensors may be used to generate sense signals which represent true signals that are part of a system. When the sensors are not calibrated, inefficiency due to offset can be introduced into a system that incorporates the generated sense signal. Flipping techniques may be used to mitigate offset. Applicant has appreciated that when the sensor gains are mismatched, the offset calibration associated with a sensor is not independent from the offset calibration associated with the other sensors. Some of the flipping techniques described herein account for gain mismatch by flipping the polarity of each sensor in a one-at-a-time fashion, and by combining the results in a common system of equations to determine the gain mismatch and the offset of each sensor.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.

Abstract: Systems and methods are provided for circuit configurations that maintain audio playback performance while reducing power consumption. In particular, a gain for a current analog-to-digital converter in an audio playback path is adjusted based on an amplitude of the input signal. Additionally, systems and methods are provided for transitioning between a modes of operation for large signals and mode of operation for small signals.

Abstract: Charge pumps with accurate output current limiting are provided herein. In certain embodiments, a charge pump includes an output terminal for providing a regulated output voltage, a switched capacitor, and switches that control connectivity of the switched capacitor to selectively charge or discharge the switched capacitor. The switches are operable in two or more phases including a charging phase in which the switched capacitor is charged with a charging current and a discharging phase in which the switched capacitor is coupled to the output terminal. The charge pump further includes an output current limiting circuit that controls the charging current to limit an amount of output current delivered by the charge pump to the output terminal. The output current limiting circuit limits the output current based on comparing a reference signal to an integral of an observation current that changes in relation to the charging current.

Abstract: Aspects of this disclosure relate to systems and methods for calibration of antenna arrays. The calibration may be based on determining a reference value for the beamformer derived from measurements of phase and/or amplitude for each channel within the beamformer. The measurements of phase and/or amplitude can be stored in non-volatile memory. Using a difference between the reference value and the measured values for each channel, a portion of a global configuration table may be copied to each channel's memory. Each channel can be separately calibrated based on the portion of the global configuration table copied to the local memory of each channel.

Abstract: A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.

Abstract: Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

Abstract: Embodiments may relate to an electronic device that includes a processor communicatively coupled with a hardware accelerator. The processor may be configured to identify, based on an indication of a priority level in a task control block (TCB), a location at which the TCB should be inserted in a queue of TCBs. The hardware accelerator may perform jobs related to the queue of TCBs in an order related to the order of TCBs within the queue. Other embodiments may be described or claimed.

Abstract: A radio timing controller equipped with one or more sequence controllers is disclosed. Sequence controllers enable high degree of programmability of the radio timing controller, e.g., in terms of the number of general purpose input/outputs (GPIOs), mapping of GPIOs to specific radio controls, setting of the radio control output states, timing to sequence events at radio symbol boundaries, etc.

Abstract: The present disclosure relates to configuring at least one pair of devices in a physical unclonable function (PUF) apparatus and reading out at least one pair of devices for determining a persistent random PUF output. The pair of devices may be readout by measuring a physical difference between the devices/components caused by random manufacturing differences, which may then be used to determine a persistence random PUF output. Configuring the pair of devices includes measuring the random manufacturing difference and, based on that measurement, setting a readout condition for the pair of devices, which dictates aspects of the readout process that should be used for that pair of devices. Each time the pair of devices is readout in the future, it may be readout in accordance with the condition that was set at configuration.

Abstract: A voltage generator circuit can be structured to provide an output voltage having a substantially flat temperature coefficient by use of a circuit loop having transistors and a resistor arranged such that, in operation, current through the resistor has a signed temperature coefficient. The current behavior can be controlled by an output transistor coupled to another transistor, which is coupled to the circuit loop, with this other transistor sized such that, in operation, a voltage of this other transistor has a signed temperature coefficient that is opposite in sign to the signed temperature coefficient of the current through the resistor. Embodiments of voltage generator circuits can also include additional components to trim output voltage, to provide unconditional stability, or other features for the respective voltage generator circuit. In various embodiments, a voltage generator circuit can be implemented as a low drop-out (LDO) voltage regulator.

Abstract: A gain stage, such as an amplifier, e.g., an instrumentation amplifier, can receive an input signal and adjust the level of the input signal, e.g., amplify or attenuate. An output voltage of the gain stage can be applied to a subsequent circuit. Using various techniques, a second stage of an instrumentation amplifier, which can include a transconductance stage that converts a current to a voltage that can be applied to an output node of the instrumentation amplifier, can be removed. Removal of such a second stage can allow an output current from the gain stage to be applied directly from a current output node to an input node of a subsequent circuit.

Abstract: A Power over Data Lines (PoDL) system provides a DC voltage and differential data signals on the same wire pair. A Powered Device (PD) load is coupled to the wire pair, via a gyrator, for being powered by the DC voltage. The gyrator emulates the DC-coupling properties of inductors using active components. The gyrator includes transistors that are controlled to act as a full-bridge rectifier for ensuring a correct polarity DC voltage is applied to the PD load. Since the transistors operate in saturation and are coupled to be insensitive to differential data signals on the wire pair, the current supplied to the PD load is substantially unaffected by the differential data signals. Negative feedback circuits in the gyrator reduce fluctuations in current through the gyrator due to differential data signals on the wire pair. No inductors are required in the gyrator. A PHY is AC-coupled to the wire pair via capacitors.

Abstract: Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to power semiconductor devices in which effects of charge trapping are compensated. A radio frequency (RF) power transmitter system comprises a RF power semiconductor device that outputs a time-varying gain characteristic from a RF signal input waveform originating from a digital input, wherein the time-varying gain characteristic includes a gain error associated with charge-trapping events having a memory effect on the RF power semiconductor device lasting longer than 1 microsecond. The RF power transmitter system further comprises circuitry configured to apply an analog gate bias waveform to the RF power semiconductor device based on the time-varying gain characteristic to reduce the gain error.