Abstract: The present disclosure relates to a PUF apparatus for generating a persistent, random number. The random number is determined by selecting one or more PUF cells, each of which comprise a matched pair of capacitors that are of identical design, and determining a value that is accurately and reliably indicative of a random manufacturing difference between them, based in which the random number is generated. The random manufacturing differences between the capacitors creates the randomness in the generated random number. Furthermore, because the random manufacturing difference should be relatively stable over time, the generated random number should be persistent.

Abstract: A power domain isolation system, such as without requiring a transformer, can include a reactive circuit, an input network having first and second input nodes that are coupled in parallel with the reactive circuit via respective first and second current control circuits, and an output network having first and second output nodes that are coupled in parallel with the reactive circuit via respective third and fourth current control circuits. The first and second current control circuits can be configured to couple the reactive circuit to the input nodes when the third and fourth current control circuits are configured to electrically isolate the reactive circuit from the output nodes, and the first and second current control circuits can be configured to electrically isolate the reactive circuit from the input nodes when the third and fourth current control circuits are configured to couple the reactive circuit to the output nodes.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Abstract: The present disclosure relates to the determination of impedances in an electrical network. Methods and apparatuses for determining one or more impedances within a root and branch network are disclosed. The impedance of a common root part and the impedance of a branch of the electrical network may be determined based on the current in the common root part, the current in a branch of the electrical network and the voltage across the common root part and the branch. By determining the impedance of different parts of the electrical network in this way, the network may be monitored over time and the location of any faults or impending faults in the network may be identified more exactly without requiring invasive network probing and testing.

Abstract: Video systems with video receivers for receiving video signals transmitted in analog format over a video link are described. An example video receiver includes an interferer identification circuit and an interferer removal circuit. The interferer identification circuit is configured to identify a periodic interference signal (e.g., from one or more of vertical blanking intervals (VBIs)) of a received video signal. The interferer removal circuit is configured to generate a filtered video signal, where generation of the filtered video signal includes, for each line of a given frame of the received video signal, generating an adjusted interference signal by adjusting a phase of the identified interference signal to match a phase of a periodic noise signal in at least a portion of a horizontal blanking interval (HBI) associated with the line, and subtracting the adjusted interference signal from a plurality of active pixel values of the line.

Abstract: Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.

Abstract: Circuits and methods for protecting against over-current conditions of switches are described. Over-current conditions can damage switches and the circuits they connect. Some embodiments of the present application provide a sense switch in parallel with the load switch. The sense switch is smaller than the load switch, and is used to sense an over-current condition of the load switch. The sense switch can remain on even when the load switch is turned off in response to detection of an over-current condition.

Abstract: A hybrid temperature sensor for an integrated circuit includes two temperature sensors—an application temperature sensor for measuring temperature during normal use of the integrated circuit, and a calibration temperature sensitive element. By providing two temperature sensitive elements within the integrated circuit, it is possible to take advantage of different characteristics of temperature sensors to achieve high accuracy calibration of the application temperature sensor relatively quickly and at low cost, whilst also maintaining desirable characteristics for the application temperature sensor, such as high speed, low power consumption, high resolution, etc.

Abstract: Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

Abstract: An example log power detector includes a gain or attenuation circuit and a detector circuit. The gain or attenuation circuit includes a plurality of gain or attenuation elements arranged in a sequence, each gain or attenuation element configured to generate an output signal that is an amplified or attenuated version of an input signal provided thereto. The detector circuit includes a plurality of detectors, each detector configured to receive the output signal from a different one of the gain or attenuation elements and to generate a signal indicative of a power of the received output signal. At least the last detector is configured to receive a DC offset signal that is different from a DC offset signal received by at least one other detector. Such a log detector may provide effective noise compensation to reduce errors caused by input noise, especially for low-power and/or high-frequency input signals.

Abstract: High power radio frequency (RF) switches with low leakage current and low insertion loss are provided. In one embodiment, an RF switch includes a plurality of terminals including an antenna terminal, a receive terminal, and a transmit terminal. The RF switch also includes a plurality of transistors that are controllable to set the RF switch in a first mode or a second mode, and an inductor electrically connected between the antenna terminal and the receive terminal.

Abstract: An antenna apparatus for calibrating one or more of a plurality of antenna elements of an antenna array using one or more probes is disclosed. The apparatus includes an upconverter and/or downconverter (UDC) circuit and a calibration arrangement that includes a switching circuit. The switching circuit is configured to enable operation of the UDC in a first mode or in a second mode. When the UDC is in the first mode, the one or more probes are electrically disconnected from the UDC circuit and the UDC may be connected to at least one of the antenna elements. When the UDC is in the second mode, at least one of the one or more probes is connected to the UDC circuit.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: Disclosed herein is a symmetric transformer in the context of a DC-DC isolated converter. The symmetric transformer reduces or eliminates asymmetry in the distribution of parasitic capacitance across the isolation barrier going from one end to another end of a primary coil, and as a result, undesirable electromagnetic interference (EMI) due to common mode dipole emission across the isolation barrier may be reduced. In some embodiments, a primary winding is split into separate first and second coils, with a serial impedance connected in between the first and second coils. The transformer is symmetric in the sense that a capacitive coupling of the first coil to a secondary winding is the same as a capacitive coupling of the second coil to the secondary winding, such that common mode EMI may be reduced.

Abstract: Different approaches that aim to extend scan range of phased array antennas by means of altering surface waves and/or altering the coupling are disclosed. One approach includes providing a phased array antenna where a surface of a substrate that houses antenna elements of the array includes openings such as trenches or grooves. Such openings in the surface effectively reduce the dielectric constant of the substrate, are easy to manufacture, and may reduce or eliminate the need to use exotic and expensive low-k dielectric materials. Another approach includes providing a phased array antenna where antenna elements are disposed over a substrate in the form of surface mount (SMT) components that are reduced in size/footprint. Using SMT antenna elements with a reduced size allows achieving the same gain while spacing antenna elements farther apart with gaps in between the antenna elements, thus also reducing the overall dielectric constant of the substrate.

Abstract: Disclosed herein is a symmetric split planar transformer in the context of a DC-DC isolated converter. The symmetric split planar transformer reduces or eliminates asymmetry in the distribution of parasitic capacitance across the isolation barrier going from one end to another end of a primary coil, and as a result, undesirable electromagnetic interference (EMI) due to common mode dipole emission across the isolation barrier may be reduced. In some embodiments, the primary winding is split into at least a first coil and a second coil, each occupying a different area side-by-side on a substrate. The transformer is symmetric in the sense that a capacitive coupling of the first coil to a secondary winding is the same as a capacitive coupling of the second coil to the secondary winding, such that common mode EMI may be reduced. Each coil may include stacked spiral coil portions in multiple metal planes to increase inductive density across the isolation barrier.

Abstract: One embodiment is a lower power technique to compensate for radio frequency (RF) amplifier gain and phase over temperature and part-to-part variation for particular use in phased array (PA) applications.

Abstract: An interface cell for circuit adjustment can be structured to adjust parameters of a circuit of an integrated circuit. The interface cell can be implemented in a small area on a die for the integrated circuit. The interface cell can be arranged for circuit adjustment, such as post package trim of the circuit. The interface cell can include a control device and a low voltage circuit. The control device can be implemented as a single device, or a device having a limited number of additional components, that interfaces a high voltage domain to a low voltage domain of the low voltage circuit. The control device can be enabled to provide the signals to the low voltage circuit of the interface cell to adjust parameters of the circuit and can be disabled to isolate the circuit from the interface cell after providing the signals to the low voltage circuit.

Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.