Abstract: The present disclosure relates to configuring at least one pair of devices in a physical unclonable function (PUF) apparatus and reading out at least one pair of devices for determining a persistent random PUF output. The pair of devices may be readout by measuring a physical difference between the devices/components caused by random manufacturing differences, which may then be used to determine a persistence random PUF output. Configuring the pair of devices includes measuring the random manufacturing difference and, based on that measurement, setting a readout condition for the pair of devices, which dictates aspects of the readout process that should be used for that pair of devices. Each time the pair of devices is readout in the future, it may be readout in accordance with the condition that was set at configuration.

Abstract: Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.

Abstract: Physical Unclonable Functions, PUFs, are hardware devices designed to generate a number that is random (i.e., two identical PUFs should produce randomly different numbers from each other) and persistent (i.e., a PUF should consistently generate the same number over time). Over time, aspects of the PUF hardware may change or drift, which may ultimately cause the generated number to change, and therefore no longer be persistent. Failure to generate a persistent number may cause difficulties for other devices that rely on the persistence of the number generated by the PUF, for example as part of a cryptographic process. The present disclosure relates to monitoring over time the physical characteristics of the PUF that are used to generate its number, and thereby keep track of its reliability to generate a random number that is persistent.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.

Abstract: Systems and methods for extracting motor operational state parameters from an electric motor for improved motor control and motor fault or failure detection are discussed. An exemplary system includes an excitation circuit to apply a drive voltage to an electric motor, and a processor circuit to measure a resulting winding current, extract a current waveform by oversampling the winding current in an entire PWM frame at a sampling rate higher than the PWM frequency, and fit the current waveform in the PWM period to a parametric model. The processor circuit can determine a motor operational state parameter using one or more of the applied drive voltage or the parametric model of the winding current.

Abstract: The present disclosure relates to a PUF apparatus for generating a persistent, random number. The random number is determined by selecting one or more PUF cells, each of which comprise a matched pair of capacitors that are of identical design, and determining a value that is accurately and reliably indicative of a random manufacturing difference between them, based in which the random number is generated. The random manufacturing differences between the capacitors creates the randomness in the generated random number. Furthermore, because the random manufacturing difference should be relatively stable over time, the generated random number should be persistent.

Abstract: Systems and methods for early-onset electrical fault detection are described in which a rate-of-rise of channel current in a device such as a transistor is sensed, indicating whether an electrical fault is present. In some embodiments, the rate-of-rise of the channel current may be sensed by detecting whether a current flowing away from a control terminal of the device is greater than a threshold level. In the event that an electrical fault is detected, the device may be shut off to prevent damage to the device.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: Circuits and methods for protecting against over-current conditions of switches are described. Over-current conditions can damage switches and the circuits they connect. Some embodiments of the present application provide a sense switch in parallel with the load switch. The sense switch is smaller than the load switch, and is used to sense an over-current condition of the load switch. The sense switch can remain on even when the load switch is turned off in response to detection of an over-current condition.

Abstract: Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.

Abstract: Disclosed herein are transimpedance circuits, as well as related methods and devices. In some embodiments, a transimpedance circuit may include a current source bias terminal, a current source output terminal, and a transimpedance amplifier coupled to the current source output terminal, wherein voltage signals at the current source bias terminal are correlated with voltage signals at the current source output terminal. In some embodiments, the current source may be a photodiode.

Abstract: A package with a laminate substrate is disclosed. The laminate substrate includes a first layer with a first terminal and a second terminal. The laminate substrate also includes a second layer with a conductive element. The laminate substrate further includes a first via and a second via that electrically connect the first terminal to the conductive element and the second terminal to the conductive element, respectively. The package can include a die mounted on and electrically connected to the laminate substrate.

Abstract: A processor system includes a processor core, a cache, a cache controller, and a cache assist controller. The processor core issues a read/write command for reading data from or writing data to a memory. The processor core also outputs an address range specifying addresses for which the cache assist controller can return zero fill, e.g., an address range for the read/write command. The cache controller transmits a cache request to the cache assist controller based on the read/write command. The cache assist controller receives the address range output by the processor core and compares the address range to the cache request. If a memory address in the cache request falls within the address range, the cache assist controller returns a string of zeroes, rather than fetching and returning data stored at the memory address.

Abstract: An example apparatus includes a power amplifier (PA) and a linearity optimizer. The optimizer includes a PA actuator and a linearity adaptation circuit. The actuator is configured to generate an actuator output based on an actuator input and a vector of complex gains computed by the linearity adaptation circuit based on a feedback signal indicative of PA's output. The adaptation circuit is configured to compute the vector of complex gains in a manner that maximizes the power of the actuator output while ensuring that the deviation of PA's behavior from a linear behavior (e.g., in terms of one or more linearity parameters) is below a threshold. Controlling actuator output in a manner that maximizes its power while taking into consideration one or more linearity parameters to ensure that target linearity is achieved controls drive signals for the PA and, thus, may help in terms of PA linearity and efficiency.

Abstract: In one aspect, a transfer function (TF) estimation circuit configured to generate an estimate of a TF undergone by signals between an input of a digital-to-analog converter (DAC) of a feedforward path of a continuous-time (CT) stage of an analog-to-digital converter (ADC) and an output of a backend ADC of the ADC is disclosed. The TF estimation circuit includes one or more circuits configured to generate a first cross-correlation output by cross-correlating digital versions of signals based on a test signal provided to the CT stage and an output signal of the backend ADC, generate a second cross-correlation output by cross-correlating digital versions of signals based on the test signal and an output signal of a quantizer of the feedforward path of the CT stage, and generate the estimate of the TF based on the first and second cross-correlation outputs.

Abstract: A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to quantize an analog input signal at an oversampled rate, and output an sigma delta modulated signal, a transposed polynomial decimator circuit to decimate the sigma delta modulated signal, and output a first decimated signal, and an integer decimator circuit to decimate the first decimated signal by an integer factor and output a second decimated signal having a desired output data rate. The transposed polynomial decimator circuit has a transposed polynomial filter circuit and a digital phase locked loop circuit, which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate, and outputs an intersample position parameter to the transposed polynomial filter circuit.

Abstract: Apparatus and methods for assisting a voltage regulator. In an example, a voltage regulator can include an error amplifier configured to compare a reference voltage with a representation of an output voltage of the voltage regulator, an output transistor coupled to a supply voltage and configured to receive an output of the error amplifier and to provide the output voltage, and an auxiliary-current circuit including a helper transistor having a terminal coupled to the output voltage, the helper transistor configured to turn on when the output voltage drops due to current demand from the load and to provide charge current to the load in addition to current provided by the output transistor.

Abstract: A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.