Abstract: A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Abstract: A MEMS sensor includes at least one closed nodal anchor along a predetermined closed nodal path on at least one surface of a resonant mass. The resonant mass may be configured to resonate substantially in an in-plane contour mode. Drive and/or sense electrodes may be disposed within a cavity formed at least in part by the resonant mass, the closed nodal anchor, and a substrate.

Abstract: In an inertial sensor having a resonator and an accelerometer, acceleration signals are induced by resonating at least one shuttle of the resonator in a device plane at a shuttle resonance mode frequency and modulating the motion of the at least one resonator shuttle to induce accelerometer signals from the accelerometer. The motion may be modulated in the device plane or out of the device plane. A shuttle resonance mode and an accelerometer resonance mode may me matched based on the induced accelerometer signals, for example, by providing a feedback signal to the inertial sensor in response to such induced accelerometer signals to substantially nullify the induced accelerometer signals.

Abstract: An apparatus for monitoring the pulse time of switches within a DC to DC power supply, comprising a timing circuit responsive to a switching confirmation signal to commence timing and to monitor for control signals being sent to the switch and to indicate whether elapsed period between the switching confirmation signal and the control signal is too long or too short.

Abstract: A measurement system includes a detector to generate a measurement signal responsive to an input signal, and a nulling circuit coupled to the detector to generate a control signal responsive to the difference between the measurement signal and a set-point signal. The nulling circuit may include a bandwidth compensation stage to maintain the overall control loop bandwidth at a substantially constant value.

Abstract: An embodiment of the present invention may be directed to a multi channel imaging system. The multi channel imaging system may include an input for a light signal and a plurality of channel circuits. Each of the channel circuits may have an analog signal processing chain converting some portion of the light signal into to a digital representation, the plurality of channel circuits may operate in parallel. The multi channel imaging system may further comprise at least one dither circuit coupled to a point in at least one of the analog signal processing chains to add dither.

Abstract: Systems and methods for increasing amplifier supply power on demand for a plurality of xDSL signals is provided. In an embodiment, circuitry may be used to detect the signal or signals having the highest voltage. In different embodiments, the signal(s) with the highest absolute voltage or highest combined voltage between complementary signal pairs may be compared to a threshold voltage, such as an existing amplifier supply voltage. In different embodiments, when these highest voltage(s) exceed the threshold voltage, the corresponding amplifier supply voltages may be increased to meet the increased amplification demand. In some embodiments when these highest voltage(s) do not exceed the threshold voltage, the amplifier supply voltage may not be increased and the existing amplifier supply voltage may be used to amplify the xDSL signals.

Abstract: Method to verify proper operation of battery monitor shift register(s). The method may be implemented on an individual battery monitor or within a system of battery monitors. Battery monitor shift register(s) may be configured to store predetermined test patterns upon start up or reset. The contents of the battery monitor shift registers may be shifted out serially to a processor or controller, which may compare the read out data to a local copy of the predetermined test pattern. If the patterns do not match, the processor or controller may indicate an error condition.

Abstract: Apparatus and methods reduce the likelihood of amplifier saturation due to propagated DC offsets, and reduce the recover from saturated stated when such saturation occurs. Advantageously, these attributes are beneficial for monitoring of bioelectric signals. A circuit uses an instrumentation amplifier connected as a high pass filter to attenuate large DC offsets and amplify small signals. The circuit can include an instrumentation amplifier electrically coupled with a first feedback circuit including at least one resistor and a second feedback circuit including an op-amp. The feedback circuit can also include a low-pass filter. The op-amp in the second feedback circuit can be configured as a non-inverting amplifier, an inverting amplifier, and/or an integrator circuit. Alternatively, the circuit can include an instrumentation amplifier with one feedback circuit including at least one resistor, and a coupling capacitor electrically coupled with a reference voltage.

Abstract: An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each test sample being obtained by inverting a single bit from the M bits, keeping other bits unaltered. Each test sample is expanded and passed through a selected low pass filter (e.g., 15 kHz) to obtain a filtered output and a differential value between the test sample and its filtered output. The test sample producing the least differential value is chosen to replace the erroneous signal sample. The technique is applicable in NICAM demodulators receiving 14 bit sample signals (at 32 kHz) companded to (N) 10 bits from which (M) 6 MSB parity encoded bits are chosen for producing test samples.

Abstract: A packaged microphone has a base with a top face, a lid coupled to the base and forming an interior, and a MEMS microphone (i.e., a die or chip) secured to the top face of the base within the interior. The packaged microphone also includes a circuit chip secured to the top face of the base within the interior. The circuit chip has a top surface with a top pad, a bottom surface with a bottom pad, and a via. The bottom pad is electrically connected to the base, and the via electrically connects the top pad with the bottom pad. A wire bond is connected between the MEMS microphone and the top pad on the circuit chip. The MEMS microphone is electrically connected to the bottom pad and the base through the via.

Abstract: A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping.

Abstract: A SOI-based MEMS device has a base layer, a device layer, and an insulator layer between the base layer and the device layer. The device also has a deposited layer having a portion that is spaced from the device layer. The device layer is between the insulator layer and the deposited layer.

Abstract: A system and method are provided for a PTAT cell with no resistors which can operate at low power, has less sensitivity to process variation, occupies less silicon area, and has low noise. Further, a system and method are provided to scale up the reference voltage and current through a cascade of unit cells. Still further, a system and method are provided for PTAT component to be fine-tuned, advantageously providing less process variability and less temperature sensitivity.

Abstract: A SOI-based MEMS device has a base layer, a device layer, and an insulator layer between the base layer and the device layer. The device also has a deposited layer having a portion that is spaced from the device layer. The device layer is between the insulator layer and the deposited layer.

Abstract: A system and method for reducing noise in resolver-to-digital converters (RDC) using a cascaded tracking loop filter. In some embodiments, one or more tracking loop filters may be implemented in a cascade to attenuate carrier harmonic frequencies in the digitized output of an RDC. Where a plurality of tracking loop filters are implemented, the output of one tracking loop filter may be input into a successive tracking loop filter.

Abstract: A drive signal for a motor-driven mechanical system has zero (or near zero) energy at an expected resonant frequency of the mechanical system. The drive signal may be provided in a series of steps according to a selected row of Pascal's triangle, wherein the number of steps equals the number of entries from the selected row of Pascal's triangle, each step has a step size corresponding to a respective entry of the selected row of Pascal's triangle, and the steps are spaced from each other according to a time constant determined by an expected resonant frequency of the mechanical system.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node.

Abstract: An active RC resonator includes a first operational amplifier having first and second inputs and first and second outputs, a second operational amplifier having first and second inputs and first and second outputs, a first resistor coupled between the first input of the first operational amplifier and the second output of the second operational amplifier, a second resistor coupled between the second input of the first operational amplifier and the first output of the second operational amplifier, a third resistor coupled between the first output of the first operational amplifier and the first input of the second input of the second operational amplifier, a fourth resistor coupled between the second output of the first operational amplifier and the second input of the second operational amplifier, and at least one of 1) a first capacitor coupled between the first input of the first operational amplifier and the first output of the second operational amplifier, and a second capacitor coupled between the second