Abstract: A method of operating a microphone system includes the steps of monitoring an I/O terminal to detect whether a signal on that terminal achieves a pre-defined logic level during a monitoring period. The I/O terminal and a second I/O terminal are configured to one of a hardware mode or a communications-bus mode depending on whether the pre-defined logic level is detected. A microphone system includes two I/O terminals and an automatic detection and mode switching circuit, as well as a communications bus interface circuit and a hardware control circuit. The mode automatic detection and mode switching circuit couples the two I/O terminals to either the communications bus interface circuit or the hardware control circuit in response to the logic level detected on one of the I/O terminals during a monitoring period.

Abstract: A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to detect the variable capacitance.

Abstract: A circuit for dissipating injected parasitic charge includes a circuit stage, a pulse generating circuit and a switch. The circuit stage has an input node and an output node that injects a parasitic charge when switched OFF to the output node. The pulse generating circuit can generate a pulsed signal having an input for receiving a control signal. The control signal indicates the circuit stage is switching OFF, and has an output for outputting a pulsed signal in response to the control signal at the input. The pulsed signal can have a predetermined duration. The switch can be configured to be actuated by the pulsed signal output by the pulse generating circuit, and has a terminal connected to the output node of the circuit stage and a terminal connected to circuit to substantially dissipate the injected parasitic charge.

Abstract: A DC-DC converter for supplying a gradually increasing voltage via a soft start circuit from a first powered domain to a second unpowered domain. The powered domain may be connected to a primary winding of a first transformer, and the unpowered domain may be connected to the secondary winding of the first transformer. The unpowered domain may respond to an applied voltage from the soft start circuit by supplying a feedback signal to the powered domain via a feedback circuit. The feedback signal indicating the power supplied from the secondary winding of the first transformer to the unpowered domain is satisfactory.

Abstract: Methods and resulting devices are disclosed related to attaching a die to a leadframe. One such method includes initially bonding a carrier pad which is pre-coated with a thermosetting first adhesive to the leadframe. The carrier pad can be electrically non-conductive. The first adhesive can be raised to its thermosetting cure temperature by heating the leadframe to a temperature just above the thermosetting cure temperature of the first adhesive. A thermosetting second adhesive which is liquid at room temperature can be applied to a second major surface of the carrier pad, and the die can be placed on the second adhesive and aligned with the leadframe. The second adhesive can be raised to its thermosetting cure temperature to bond the die to the carrier pad, and in turn form a bonded assembly.

Abstract: A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.

Abstract: Apparatus and methods of trimming resistors are disclosed. In one embodiment, a method of controlling the PCR of a thin film resistor is provided. The method includes applying a first current to a resistor so as to alter a property of the resistor, and measuring the property of the resistor. Applying the first current and measuring the property of the resistor can be repeated until the PCR of the resistor is within an acceptable tolerance of a desired value for the property of the resistor.

Abstract: A detector circuit includes a main path having a first detector to generate an output signal in response to an input signal, and a reference path having a second detector matched to the first detector to generate a reference signal in response to the input signal. The reference signal may be used to compensate the output signal for variations in operating frequency, temperature, or the like. The reference path may be arranged to reuse a signal available in the main path so that the signal applied to the second detector experiences the same operating effects as that applied to the first detector.

Abstract: An analog-to-digital converter system that includes a pipeline including N successively-cascaded signal converters, each converting, according to a first clock signal, a respective portion of an input signal of the pipeline into digital codes, a code aligner for receiving and aligning the digital codes from the signal converters in the pipeline into a digital output of the system, an error extractor coupled to an amplifier input node of a selected one signal converter via a first switch for extracting an error signal, and a load system coupled to the amplifier input node of the selected one signal converter via a second switch.

Abstract: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly.

Abstract: A method and system that may include a pair of amplifier transistors and an output coupled to a load device. The precharge buffer may be controlled by an activation signal. The precharge buffer may also include a pair of level shifters. Each level shifter may be provided in association with a respective one of the transistors, and each may provide a respective level shift to an input signal at a common signal source based on a reference voltage. Outputs of the level shifters may be coupled to the respective transistors. The precharge buffer may also include a bypass signal path extending from the common signal source to the load device. A signal path may be controlled by another activation signal, and the precharge buffer and the bypass signal may be enabled during mutually exclusive states of the activation signal.

Abstract: Temperature-compensation network embodiments are provided to generate compensation signals which may be useful in improving the performance of a variety of important systems. An embodiment includes a limit current mirror configured to provide a limit current, a current generator to provide a slope current whose magnitude varies with temperature, and an output current mirror positioned to receive the limit current and the slope current and configured to provide a compensation current. In addition, a floating voltage reference is provided for use in various networks which include the temperature-compensation networks. The temperature-compensation networks may be used to improve performance in systems such as a panel driver which provides turn-on and turn-off gate voltages to transistors in liquid crystal displays.

Abstract: A voltage regulator comprises first and second bipolar transistors operating at different current densities; a resistance is connected between their bases across which ?VBE appears. A third bipolar transistor is connected such that its base voltage is equal to that of the first transistor or differs by a PTAT amount. A current mirror balances the collector current of one of the second and third transistors with an image of the collector current of the first transistor when an output node is at a unique operating point. The operating point includes both PTAT and CTAT components, the ratio of which can be established to provide a desired temperature characteristic. A feedback transistor provides current to the bases of the bipolar transistors and to the output node and is driven by the current mirror output to regulate the voltage at the output node by negative feedback.

Abstract: A packaged microphone has a base, a lid coupled to the base forming an interior, a MEMS microphone secured to the base within the interior, and an integrated circuit embedded in the base. Apertures in the base and integrated circuit are aligned to form an aperture from the exterior of the package to the interior.

Abstract: An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.

Abstract: Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a lower impedance than the second switch. When a wake up signal is received, the second switch may be turned on first and the first switch may be turned on after the virtual power supply reaches a predetermined voltage level.

Abstract: A micro-machined switching system for equalizing an electrical property, such as charge due to parasitic capacitance formed at an input and an output of a micro-machined switching device. The micro-machined switching device may be a MEMS relay or a MEMS switch. In addition to the micro-machined switching device, the switching system also includes a balancing module for equalizing the electrical property between the input and the output of the micro-machined switching device. In certain embodiments, the balancing module includes a switch operable in a first state causing charge due to the parasitic capacitance on the input and the output of the micro-machined switching device to substantially balance. The switch is also operable in a second state wherein parasitic capacitance can separately accumulate at the input and the output of the micro-machined switching device.

Abstract: A digital output sensor includes a sensor module for providing digital data representative of a sensed parameter, a First-In-First-Out (FIFO) memory having a single port memory, and an output port for transmitting the digital data. The digital data from the sensor module is pushed into the FIFO memory buffer via the single memory port, and the digital data is popped out of the FIFO memory buffer via the single memory port for receipt by the output port.

Abstract: A force/sense voltage-mode DAC coupled with multiple transconductance amplifiers that generate a correction current injected to a node in one of the DAC cells is discussed. The correction current injected into the DAC cell may reduce nonlinearity produced by biasing current to the operational amplifiers in the DAC.

Abstract: A mode matching servo for an inertial sensor having a resonator and an accelerometer provides a test signal at a frequency higher than a predetermined inertial sensor response frequency and lower than an accelerometer resonance mode frequency so as to induce acceleration signals from the accelerometer substantially at the test signal frequency when the modes are not matched. A feedback signal is provided in response to such induced signals to substantially nullify the signals.