Abstract: Embodiments may relate to an electronic device that includes a processor communicatively coupled with a hardware accelerator. The processor may be configured to identify, based on an indication of a priority level in a task control block (TCB), a location at which the TCB should be inserted in a queue of TCBs. The hardware accelerator may perform jobs related to the queue of TCBs in an order related to the order of TCBs within the queue. Other embodiments may be described or claimed.

Abstract: A voltage converter circuit comprises a charge pump circuit, a pulse width modulation (PWM) filter stage circuit, and a control circuit. The charge pump circuit includes multiple switching transistors arranged as a switching bridge including a first bridge portion connected to a second bridge portion; a midpoint capacitor connected to a circuit node coupling the first bridge portion and the second bridge portion; and a first flying capacitor coupled to the first bridge portion and the second bridge portion. The PWM filter stage circuit is coupled to the charge pump circuit and a first input/output terminal and includes a first inductor coupled to the first flying capacitor and the second bridge portion of the switching bridge. The control circuit is configured to control activation of switching transistors of the switching bridge to generate a regulated voltage at the first input/output terminal.

Abstract: Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

Abstract: Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) circuit comprises N weighted bit capacitors, wherein N is a positive integer greater than one; a sampling circuit configured to sample an input voltage onto the N weighted bit capacitors; and logic circuitry. The logic circuitry is configured to enable sampling of the input voltage onto the N weighted bit capacitors in a high-resolution mode; enable sampling of the input voltage onto N?M of the weighted bit capacitors in a low-resolution mode and sampling a common mode voltage onto the most significant M weighted bit capacitors, wherein M is a positive integer greater than zero and less than N; and initiate successive bit trials using the weighted bit capacitors to convert the sampled input voltage to a digital value.

Abstract: A power device can be structured with a power switch having multiple arrangements such that the power switch can operate as a power switch with the capability to measure properties of the power switch. An example power device can comprise a main arrangement of transistor cells and a sensor arrangement of sensor transistor cells. The main arrangement can be structured to operate as a power switch, with the transistor cells of the main arrangement having control nodes connected in parallel to receive a common control signal. The sensor arrangement of sensor transistor cells can be structured to measure one or more parameters of the main arrangement, with the sensor transistor cells having sensor control nodes connected in parallel to receive a common sensor control signal. The sensor transistor cells can have a common transistor terminal shared with a common transistor terminal of the transistor cells of the main arrangement.

Abstract: In a wireless mesh network having multiple network managers, the network managers maintain network security through the use of encryption keys and packet counters. To ensure that each network manager can authenticate communications with any node of the network, the authentication data is replicated in a disjoint manner in all network managers. Advantageously, network reliability is assured by providing redundant managers that can seamlessly maintain network operation even if multiple network managers fail; newly joining managers can obtain full authentication data for the network upon joining; and network throughput is increased by ensuring that any of the multiple managers can authenticate the communications of any network node. The disjoint replication of the authentication data across all network managers is performed with low data-rate manager-to-manager packets propagated through the network.

Abstract: A MEMS resonant accelerometer includes two proof masses configured to resonate when driven with periodic signals. Each proof mass includes a resonator structure that vibrates relative to the proof mass and a dummy structure that does not resonate. When driven by a periodic drive signal, the resonator structures of the two proof masses may be used to determine the magnitude of acceleration in the direction perpendicular to the planes of the proof masses by sensing the frequency at which the resonators vibrate. For example, a differential oscillation frequency may be computed from the two sensed frequencies. The dummy structures are used to make the mass distribution of the two proof masses similar.

Abstract: An example current mirror arrangement includes a first portion and a second portion, each of which includes a current mirror having transistors Q1 and Q2, a buffer amplifier that has an input coupled to a base/gate terminal of Q1 and an output coupled to a base/gate terminal of Q2, a master resistor coupled to an emitter/source terminal of Q1, and a slave resistor coupled to an emitter/source terminal of Q2. Furthermore, the slave resistor of the first portion is coupled to the slave resistor of the second portion. Providing additional resistors on master and slave sides of a current mirror arrangement may advantageously allow benefiting from the use of buffers outside of a feedback loop of a current mirror while reducing the sensitivity of the current mirror arrangement to buffer offsets.

Abstract: An apparatus that implements DPD in a manner that can address OOB instability issues, PE instability issues, or both, is disclosed. The apparatus includes an actuator circuit configured to use a model of a power amplifier (PA) to apply a predistortion to at least a portion of an input signal, and an error correction circuit configured to generate an error signal indicative of a deviation of the output of the actuator circuit from the target output, e.g., in terms of OOB or PE. The apparatus also includes an adaptation circuit configured to update the model based on the error signal. By using such an error in adapting the model used for the DPD, undesirable effects of performing DPD, such as creation or amplification of OOB frequency components, or increasing amplitude of some samples, may be reduced or eliminated.

Abstract: Differential sampling circuits may be adversely affected by changes in common mode voltage. Changes in the common mode voltage may alter the on resistance of transistor switches which it turn may mean that small signal changes are not correctly observed against a bigger common mode signal. The present disclosure relates to a way of improving the ability to resolve small differential signal changes by varying the supply or drive voltage to a component to compensate for common mode voltage changes.

Abstract: Techniques are provided for an integrated circuit, current loop interface that can receive and extract a high-frequency digital communication signal from a low-frequency analog current signal using a complex impedance circuit. The complex impedance circuit can allow for low input impedance at the lower frequencies of the analog current signal and high input impedance at the higher frequencies of the digital communication signal.

Abstract: An integrated gesture sensor module includes an optical sensor die, an application-specific integrated circuit (ASIC) die, and an optical emitter die disposed in a single package. The optical sensor die and ASIC die can be disposed in a first cavity of the package, and the optical emitter die can be disposed in a second cavity of the package. The second cavity can be conical or step-shaped so that the opening defining the cavity increases with distance from the upper surface of the optical emitter die. The upper surface of the optical emitter die may be higher than the upper surface of the optical sensor die. An optical barrier positioned between the first and second cavities can include a portion of a pre-molded, laminate, or ceramic package, molding compound, and/or metallized vias.

Abstract: Capped microelectromechanical systems (MEMS) devices are described. In at least some situations, the MEMS device includes one or more masses which move. The cap may include a stopper which damps motion of the one or more movable masses. In at least some situations, the stopper damps motion of one of the masses but not another mass.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.

Abstract: Optical systems can emit train(s) of light pulses onto objects to derive a distance between the light source and the object. Achieving meter or centimeter resolution may require very short light pulses. It is not trivial to design a circuit that can generate narrow current pulses for driving a diode that emits the light pulses. An improved driver circuit has a pre-charge path comprising one or more inductive elements and a fire path comprising the diode. Switches in the driver circuit are controlled with predefined states during different intervals to pre-charge current in the one or more inductive elements prior to flowing current through the fire path to pulse the diode.

Abstract: A phase shifter that includes an RF splitter is disclosed. The RF splitter is arranged so that an RF input signal is provided to, and split over portions of, a feed line that connects an antenna element with a radio transmitter/receiver/transceiver, thus realizing a feed line splitter. Feed line splitters described herein are provided with switches that allow changing a point at which the RF input signal is fed to the feed line, where the switches may be semiconductor-based or MEMS-based switches. The point at which the RF input signal is provided to the feed line to be split defines the electrical path length that the RF energy will travel down each respective path of the feed line splitter, which, in turn, changes the phase shift realized at each output of the feed line splitter. Different antenna elements may be coupled to different outputs of the feed line splitter.

Abstract: Single-axis teeter-totter accelerometers having a plurality of anchors are disclosed. The plurality of anchors may be arranged about a rotation axis of the teeter-totter proof mass. Each of the plurality of anchors may be coupled to the proof mass by two torsional springs each extending along the rotation axis. The plurality of anchors allows an increased number of torsional springs to be coupled to the proof mass and thus greater torsional stiffness for the proof mass may be achieved. Due to the higher torsional stiffness, the disclosed single-axis teeter-totter accelerometers may be deployed in high-frequency environments where such increased torsional stiffness is required, for example, around 20 kHz and above.