Abstract: Techniques for a sinking and sourcing power stage are provided. In an example, a power stage circuit can include a first power transistor configured to couple to a first input power rail, a second power transistor configured to couple to a second input power rail, an output node configured to couple to a load and to couple the first power transistor in series with the second power transistor between the first and second input power rails, and a controller configured to operate the first and second power transistors in a first mode to source current to the load and to operate the first and second power transistors in a second mode to sink current from the load.

Abstract: A measurement circuit is arranged to make several measurements, either at different times or in respect of different frequency components of currents measured by current sensors in respective phases of a multiphase supply system. The measurements are then used to correct for discrepancies in the transfer function of the sensors.

Abstract: A microelectromechanical system (MEMS) device is provided that includes a substrate having a dielectric cavity formed therein and a movable electromechanical device suspended in the dielectric cavity. The dielectric cavity includes a substantially planar bottom surface and at least one sidewall surface extending substantially perpendicularly from the bottom surface. The movable electromechanical device is suspended in the dielectric cavity such that the movable electromechanical device is spaced apart from the bottom surface and the at least one sidewall surface of the dielectric cavity. The bottom surface of the cavity and each of the at least one sidewall surface of the cavity meet at a rectilinear corner.

Abstract: A current mirror arrangement with a current mirror and a double-base current circulator is disclosed. The current mirror is configured to receive an input current (IIN) and generate a mirrored current (IM), where IM=K*IIN. The current circulator, coupled to the current mirror, is configured to convey the mirrored current to an output node of the arrangement. The current circulator is a double-base current circulator and includes a first branch configured to receive a first branch current (I1b), where I1b=m*IM, where m is a positive number less than 1, and further includes a second branch configured to receive a second branch current (I2b), where I2b=(1?m)*IM. The first branch includes a cascode of transistors Q3 and Q5, configured to provide I1b to an output node. The second branch includes a transistor Q4 configured to provide I2b to the output node, where it is combined with I1b.

Abstract: Techniques for saving operating power of an analog-to-digital converter (ADC) are provided. In an example, a circuit can include an ADC configured to provide a multiple-bit digital representation of an analog input during a first mode of operation and an output configured to provide a single bit representation of a first comparison of the analog input signal to a second analog signal during a second mode of operation. In certain examples, the circuit can include an encoder configured to provide the multiple-bit digital representation during the first mode and to power down during the second mode of operation.

Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Abstract: Optically isolated micromachined (MEMS) switches and related methods are described. The optically isolated MEMS switches described herein may be used to provide isolation between electronic devices. For example, the optically isolated MEMS switches of the types described herein can enable the use of separate grounds between the receiving electronic device and the control circuitry. Isolation of high-voltage signals and high-voltage power supplies can be achieved by using an optical isolator and a MEMS switch, where the optical isolator controls the state of the MEMS switch. In some embodiments, utilizing optical isolators to provide high voltages, the need for electric high-voltage sources such as high-voltage power supplies and charge pumps may be removed, thus removing the cause of potential damage to the receiving electronic device. In one example, the optical isolator and the MEMS switch may be co-packaged on the same substrate.

Abstract: Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. To meet high performance requirements, the input circuitry is typically implemented with power hungry circuitry in a different semiconductor technology from the analog-to-digital converter that the input circuitry is driving. With suitable optimization techniques, performance requirements on the input circuitry can be reduced while meeting target performance of the receiver signal chain. Specifically, optimization techniques can compensate for input frequency-dependent properties and/or amplitude-dependent properties of the input circuitry. In some cases, reducing performance requirements on the input circuitry means that the input circuitry can be implemented in the same semiconductor technology as the analog-to-digital converter.

Abstract: A multiphase switching converter includes a first switching converter circuit including a power stage coupled to a DC voltage supply and a controller. The controller includes an over-current (OC) circuit that can detect an OC event and, upon detecting the OC event, set a command signal to a preset low value and provide a first hiccup signal. A synchronization circuit can generate a second hiccup signal based on the command signal of the OC circuit satisfying a first reference threshold value, and a sampled portion of an output voltage of the power stage satisfying a second reference threshold value. A hiccup timer can be triggered by one of the first hiccup signal or the second hiccup signal to start a hiccup pulse in response to being triggered.

Abstract: Device for improving an optical detecting smoke apparatus and implementing thereof. Apparatus and methods for detecting the presence of smoke in a small, long-lasting smoke detector are disclosed. Specifically, the present disclosure shows how to build one or more optimized blocking members in a smoke detector to augment signal to noise ratio. This is performed while keeping the reflections from the housing structure to a very low value while satisfying all the other peripheral needs of fast response to smoke and preventing ambient light. This allows very small measurements of light scattering of the smoke particles to be reliable in a device resistant to the negative effects of dust. In particular, geometrical optical elements, e.g., cap and optical defection elements, are disclosed.

Abstract: Systems and methods involving nanomaterial-based electrodes, such as supercapacitor and battery electrodes that can be flexible, are described.

Abstract: Disclosed herein are some examples of algorithmic analog-to-digital converters (AADCs) that perform noise shaping. In particular, an AADC disclosed herein includes circuitry that can store residue(s) of one or more conversion cycles produced by the AADC and apply a value corresponding to the residue(s) to a subsequent conversion cycle. The AADC may perform a filtering procedure with the residue(s) to produce the value applied to the subsequent conversion. Applying the value to the subsequent conversion cycle can increase a signal-to-noise ratio of the signal that the AADC is converting in the subsequent conversion cycle.

Abstract: A multi-input analog-to-digital converter (ADC), i.e., a single ADC, can receive multiple analog input signals and generate multiple digital outputs. To combine multiple analog input signals into a single multi-input ADC, the multi-input ADC would typically include multiple track and hold (T/H) circuits and an adder, which can consume a significant amount of power and incur large cost overhead. An improved approach is to combine multiple inputs through a unique T/H circuit in the front-end of the ADC. The multiple analog input signals can be aggregated using code sequences, without requiring a significant amount of external circuits.

Abstract: Aspects of this disclosure relate to detecting a header of a packet. A receive signal path can provide a receive signal that includes packets and a guard preamble between successive packets of the packets. A receiver control circuit can trigger a timer that sets a time for detecting a header of a packet in response to detecting an end of a preamble of the packet.

Abstract: Aspects of the embodiments are directed to passive depth determination. Initially, a high power depth map of a scene can be created. An object in the scene can be identified, such as a rigid body or other object or portion of an object. A series of lower power or RGB images can be captured. The object can be located in one or more of the lower power or RGB images. A change in the position of an object, represented by a set of pixels, can be determined. From the change in position of the object, a new depth of the object can be extrapolated. The extrapolated depth of the object can be used to update the high power depth map.

Abstract: According to various aspects, a delay-based physical unclonable function (PUF) device is provided. According to one embodiment, the PUF device includes circuitry for generating output bits of entropy by comparing, or “racing”, a plurality of PUF cells. A PUF cell is a building block of the PUF device. For example, the PUF device may include two identically designed circuits with only process related variations and each circuit can be a PUF cell. According to another aspect, if PUF cells with same history of winning or losing are being compared in a race, adversaries cannot predict the outcome of the current race based on previous race results. Accordingly, systems and methods are described herein for generating multiple rounds of races based on the previous rounds of races. Thus, one PUF cell can be used in multiple pairwise comparisons while maximal entropy is extracted.

Abstract: A reference buffer circuit comprises a dual-difference amplifier circuit including a first differential input, a second differential input, and a differential output that provides a differential reference signal; a first reference voltage coupled to a first input of the first differential input and a second reference voltage coupled to a first input of the second differential input; and wherein outputs of the differential output are connected by a feedback circuit path to second inputs of the first and second differential inputs.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: There is disclosed in one example a circuit for measuring impedance, including: a current mirror including a first current path and a second current path; a sensor having a terminal electrically coupled to the first current path of the current mirror circuit; a charge collector electrically coupled to the second current path of the current mirror; and an analog-to-digital converter to output a digital value of charge on the charge collector over a known time, wherein the digital value corresponds to an impedance of the sensor.