Abstract: A multi-input operational amplifier comprises two transconductors, two current mirrors, and a current source. Each transconductor generates a current according to a corresponding voltage difference. When the voltage difference is less than or equal to zero, the current is a constant. When the voltage difference exceeds zero, the current is proportional to the voltage difference.

Abstract: A slope rate compensation circuit includes a source follower level-shift amplifier, a capacitor, a first resistor and a second resistor. The source follower level-shift amplifier includes a first transistor and a second transistor. The first transistor allows a first current to flow therein, the second transistor allows a second current to flow therein, and the first current increases with the second current. The capacitor is connected to the source terminal of the first transistor. The first resistor is connected to the source terminal of the second transistor. The second resistor allows a third current to flow therein, and the third current increases with the second current. The second resistor is related to the output voltage of the slope rate compensation circuit.

Abstract: A PWM controller for controlling a switching voltage regulator comprises a first comparator, a second comparator and a third comparator. The first comparator is configured to detect voltages of a first node and a second node so as to determine whether to stop the PWM controller. The PWM controller is stopped if a first potential is lower than a threshold, and the first potential derives from the voltage of the first node by a level shift of a first voltage difference. The second comparator is configured to detect the voltage of the first node and then to compare the voltage with a power reference voltage so as to determine whether the PWM controller receives necessary power. The third comparator is configured to compare the voltage of the second node with an enable reference voltage so as to determine whether to disable the PWN controller.

Abstract: A pulse width modulation controller comprises a disabling unit, a level sensor and an over current protector. These three devices are all coupled to a multi-function node for accomplishing a disable function, input level sensing, and over-current protection, respectively.

Abstract: A control circuit comprises a PWM control circuit and a PWM skip control circuit. The PWM control circuit controls a switching circuit. The switching circuit acts as a current source for an output circuit and a load circuit. The PWM skip control circuit controls the operation of the PWM control circuit. When the output current of the switching circuit is below a predetermined threshold, the PWM skip control circuit stops the operation of the PWM control circuit. When the output voltage of the switching circuit is below a predetermined threshold, the PWM skip control circuit resumes the operation of the PWM control circuit.

Abstract: A clamp circuit comprises a first transistor, a second transistor and a voltage-dividing circuit. The first transistor has a source terminal connected to a reference voltage, and has a drain terminal grounded through a current source. The second transistor has a gate terminal connected to the gate and drain terminals of the first transistor, and has a drain terminal grounded. The voltage-dividing circuit is connected to an input voltage end, an output voltage end and a source terminal of the second transistor for providing a clamping voltage.

Abstract: A PWM controller applied to a switching voltage regulator comprises a disabling circuit, a power-sensing circuit, an over-current protection circuit and a PWM logic circuit. The disabling circuit is connected to an external frequency compensation circuit for detecting a voltage used to stop the operation of the PWM controller. The power-sensing circuit is configured to stop the operation of the PWM controller if the input voltage of the high side switch is lower than a threshold. The over-current protection circuit is configured to monitor current flowing through the output circuit, and the over-current protection circuit generates an over-current protection signal when the current exceeds a threshold. The PWM logic circuit is connected to the outputs of the disabling circuit, power-sensing circuit and over-current protection circuit.

Abstract: The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor.

Abstract: A sampling circuit includes an input voltage source; a first switch having an input operatively connected to the input voltage source; a sampling capacitor operatively connected to an output of the first switch; an operational amplifier having an inverting input operatively connected to the sampling capacitor; a second switch operatively connected across the inverting input of the operational amplifier and an output of the operational amplifier; and a second capacitor operatively connected to the output of the first switch. The first switch has a variable parasitic capacitance, and the second capacitor has a substantially more linear capacitance than the variable parasitic capacitance and is in parallel with the variable parasitic capacitance. A combined variable parasitic capacitance and capacitance of said switch capacitor is more linear than the variable parasitic capacitance of the first switch.

Abstract: A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.

Abstract: A sampled-data analog circuit uses zero-crossing detector. A waveform generator produces a plurality of segments of ramp at the output. An output of a zero crossing detector controls a sampling switch, thereby causing a precise sample of the output voltage to be taken at the instant the zero crossing detector senses the zero crossing of the input signal. The waveform generator further includes a output hold function to maintain the output voltage.

Abstract: The oscillation circuit includes an output current mirror, a P-N complementary current mirror, a P-type current mirror and an N-type current mirror. The P-N complementary current mirror has the same structure as the output current mirror but has current that is only 1/k times the current of the output current mirror, wherein k is greater than 1. The P-type current mirror connects to the P-N complementary current mirror, and has current that is m times the current of the P-N complementary current mirror, where m is greater than 1. The N-type current mirror has one end connected to the P-type current mirror and another end connected to the output current mirror. The N-type current mirror has current that is n times the current of the P-type current mirror, where m × n k ? 1 , and n is greater than 1.

Abstract: The power transistor circuit with high-voltage endurance includes a first power transistor, a second power transistor and an enabling circuit. The first power transistor includes a first voltage endurance and a first inner resistance, while the second power transistor includes a second voltage endurance and a second inner resistance. The first voltage endurance and the first inner resistance are smaller than the second voltage endurance and the second inner resistance, respectively. The drain of the second power transistor is connected to the drain of the first power transistor and the enabling circuit. The enabling circuit enables the second power transistor first, and when the drain voltage of the first power transistor is smaller than the first endurance, the enabling circuit then enables the first power transistor.

Abstract: A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit can keep the output common-mode voltage substantially constant.

Abstract: The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit.

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract: A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit can keep the output common-mode voltage substantially constant.

Abstract: The low voltage circuit for starting up a synchronous step-up DC/DC converter, which connects to a voltage source through an inductor, includes a P-type power transistor, an N-type power transistor and a controller. The P-type power transistor includes a body diode, and one end of the P-type power transistor acts as a power source of an oscillator. The N-type power transistor connects the P-type power transistor in series, and both of the power transistors are not enabled at the same time. The oscillator electrically connects to the controller, which enables the P-type power transistor at initialization time, and enables the N-type power transistor a period after the initialization time.

Abstract: The switching method between pulse frequency modulation and pulse width modulation signals is first based on an output voltage of a power transistor to generate a corresponding pulse frequency modulation signal. Next, it is determined whether the corresponding pulse frequency modulation signal has reached its maximal frequency. If so, the initial pulse width modulation signal is adjusted to have the same width as the pulse frequency modulation signal. Thereafter, the adjusted pulse width modulation signal is outputted.

Abstract: The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor.