Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.

Abstract: A semiconductor package having a light, thin, simple and compact structure including outer leads having a minimum length and a resin encapsulate having a minimum volume. The semiconductor package includes a package body, a semiconductor chip mounted on a central portion of the body, inner and outer leads bonded to a peripheral portion of an upper surface of the body by an insulating layer in such a manner that the leads are supported on the body, conductive wires or bumps for electrically connecting the inner leads to the semiconductor chip, a resin encapsulate for encapsulating the semiconductor chip, the conductive wires or bumps and the inner leads. Each outer lead has an end positioned at a level higher than an upper surface of the semiconductor chip so that a boundary portion defined between the associated outer and inner leads serves as a barrier for the resin encapsulate. The end of each outer lead is exposed outside the resin encapsulate and extending to a peripheral edge of the body.

Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.

Abstract: A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

Abstract: A method of manufacturing an alumina-silicon carbide nanocomposite having particular application to improved ball bonding capillaries of a wire bonding device produces a structure with a 93-98 volume percent of .alpha.-alumina having an average diameter of 0.1-0.3 .mu.m, a 2-7 volume percent of .beta.-silicon carbide having an average diameter of 0.1-1.5 .mu.m, a bending strength of 340-550 Mpa, and a toughness of 3.3-4.1 Mpam.sup.1/2.

Abstract: A unit printed circuit board (PCB) carrier frame used in the fabrication of a heat sink-attached ball grid array (BGA) semiconductor packages and a method for BGA semiconductor packages using the unit PCB carrier frame. The unit PCB carrier frame has a plurality of die pads each defined at its peripheral edges by elongated slots formed at a strip or reel-shaped frame member. For the fabrication of heat sink-attached BGA semiconductor packages, unit PCBs are bonded to the die pads of the unit PCB carrier frame. Accordingly, the bending of the packages is minimized even when they pass through subsequent processes requiring a high temperature. As a result, it is possible to obtain a maximum number of unit PCBs from a PCB panel, thereby achieving an improvement in productivity.

Abstract: A wafer map conversion method capable of converting a format file, which includes data about a wafer obtained by category grades through a wafer testing device and all information associated with the wafer in accordance with a certain format, into a configuration file or standard file which can be practically applied to a die bonding device, thereby easily checking the content of the process through a processing mode translated from the configuration file or standard file. Practically, the die bonding process for good-grade dies by grade levels can be achieved based on BCE data. It is also possible to perform the die bonding process in accordance with a certain map format without requiring any test for the wafer memory and dies. Only selected dies can be processed without requiring an alignment and test for every die. Accordingly, a great improvement in the process quality is obtained. An improvement in yield in processing rate (UPH) is also achieved.

Abstract: A heat sink-integrated semiconductor package is fabricated by a characteristic method comprising the steps of dispensing a liquid epoxy resin over at least the bare surface of a heat sink mounted with a semiconductor chip, curing said dispensed liquid epoxy resin to form a first encapsulating part so as to prevent delamination at the interface between said heat sink and said semiconductor chip, molding a mold compound to form a second encapsulating part to protect said package from the external environment. The semiconductor package of the present invention, the first encapsulating part is of stronger bonding strength than the second encapsulating part, so that the delamination phenomenon at the interface between heat sink and semiconductor chip can be prevented or relieved efficiently.

Abstract: A printed circuit board (PCB) having an epoxy barrier disposed around its throughout slot in a semiconductor chip mounting region, and a BGA semiconductor package using such a PCB, thereby exhibiting a high moisture discharge characteristic. The epoxy barrier includes a copper layer and a solder resist layer both disposed around the throughout slot and is defined by a groove which is disposed around the throughout slot while spacing apart from the periphery of the throughout slot by a desired distance. Alternatively, the epoxy barrier includes a solder resist layer formed to a desired width around the throughout slot on the uppermost layer laminated on the PCB. By virtue of the epoxy barrier, the throughout slot is not closed by epoxy resin coated over the PCB. As a result, it is possible to externally discharge moisture which expands in the PCB upon carrying out a series of processes for the fabrication of the package at a high temperature or mounting the package on a mother board.

Abstract: A power drawing circuit for a two-wire switching unit, the two-wire switching unit including a switching control circuit having its positive voltage input terminal connected in series to a load, the load being connected to one side of a power source.

Abstract: This invention is related to providing a bonding method for flip chips in which the circuit part is oriented to be face-down on a substrate after bonding bumps are formed on the semiconductor chip namely, forming Au bumps by Au wire ball bonding employing a wire ball bonding device onto aluminum bond pads of the semiconductor chips; coating the Au bumps with Sn/Pb alloy bumps also by wire ball bonding using a wire ball bonding device; with or without re-forming the Sn/Pb alloy bumps into a desired ball-shape by performing a heat treatment in a furnace after an activation solvent is applied to the Sn/Pb alloy bumps; and bonding (by the heat treatment in the furnace) the substrate to the coated bumps containing chip by a heat treatment in the furnace.

Abstract: A lead frame for semiconductor packages is disclosed. In the lead frame, some of the inner leads in the four sides are extended and provided with connection bars on their inside ends. Alternatively, diagonally arranged tie bars of the lead frame are extended and provided with a rectangular guide ring on their inside ends. The connection bar or guide ring functions as a dam for restricting possible overflow of adhesive, which adhesive is applied on the heat sink for bonding a semiconductor chip to the heat sink. The lead frame of the invention also prevents waste of expensive tape by letting the adhesive tape adhere only to the connection bars or to a given portion of the guide ring when mounting the lead frame to the heat sink and makes it possible higher integration of semiconductor chip by making connection bar and guide ring from the lead or the tie bar.

Abstract: A method for checking wire bonding result of a ball grid array (BGA) package is disclosed. An electroconductive metal layer of gold or copper is grounded on a chip bonding portion of a printed circuit board (PCB) of the BGA package as well as on a passage extending between the chip bonding portion and the gate of the PCB. After a wire bonding step, a probe and a capillary of a wire bonding checking system contact with the gate and with a semiconductor chip respectively. Thereafter, an electric current is sent to the BGA package from the checking system so as to check whether the BGA package sends the electric current therethrough. When there is neither a lift bond nor a missing wire in the BGA package, the package will send the current. However, when there is either a lift bond or the missing wire in the BGA package, the package will not send the current.

Abstract: A BGA (ball grid array) semiconductor package with a ring-type heat sink is disclosed. In the above package, the heat dissipating area is enlarged by extending the edge of a chip mounting die paddle formed of a copper or copper alloy layer to the outside of the package. The ring-type heat sink is attached to the extended portion of the die paddle such that the heat sink surrounds the encapsulant of the package. The above BGA package thus directly and effectively dissipates the chip's heat through the heat sink with high thermal conductivity. A plurality of plated through holes may be formed on the chip mounting portion of the PCB of the above package. The BGA package with both the ring-type heat sink and the PTHs, the heat dissipating effect of the package is further improved.

Abstract: A chip mounting plate construction of lead frames for semiconductor packages which provides a chip mounting plate having a greatly reduced area to obtain a small bonding area between the chip mounting plate and a semiconductor chip mounted on the chip mounting plate, thereby capable of minimizing thermal strain generated at the chip mounting plate due to a thermal expansion thereof. The chip mounting plate is constructed to have a smaller area than the semiconductor chip, to have a central opening, or to have recesses.

Abstract: Method and circuit board structure for leveling the tops of solder balls of a BGA semiconductor package is disclosed. In order to level the solder balls, the sizes of solder ball lands used for welding the solder balls to the circuit board are controlled in accordance with portions of the circuit board. The invention thus achieves the coplanarity of the solder balls regardless of thermal bending of the plastic body and circuit board of the BGA semiconductor package. In an embodiment, a plurality of solder ball lands having different sizes are formed on the circuit board prior to forming the solder balls on the lands. In another embodiment, a plurality of solder ball lands having the same size are formed on the circuit board prior to forming an insulating mask on the circuit board in order to form differently-sized exposed inside portions of solder ball lands.