Abstract: The present invention includes a method, system, and apparatus for providing communication control. The invention includes a method in which signaling is processed externally to a switch before it is applied by the network elements. The processor is able to select network characteristics and signal the network elements based the selections. A network employing the processing method is also included, as well as a signaling system that employs the processing method.

Abstract: The invention provides a reliable write method of data on an optical record carrier without changing the conventional configuration of an information recording apparatus. The invention uses the errors occurred in reading ATIP codes and/or the reflected signal from the surface of the record carrier to decide if the storage unit on the record carrier is eligible to store data. The defective storage units are labeled as unrecordable.

Abstract: A method for qualifying a local loop for digital subscriber line service includes transmitting signals from a customer modem and receiving corresponding reflected signals. The loop qualification test is initiated at the customer side, with the test result for the loop qualification test being based on reflected signals that correspond to signals transmitted over the loop from the modem.

Abstract: An optimization algorithm is provided for linear prediction based speech coding systems. The optimization algorithm minimizes the error between original speech samples and synthesized speech samples. Optimized linear prediction coefficients are computed directly from a system difference equation without converting the coefficients into the root-domain.

Abstract: An antenna array formed on a deformable dielectric material or substrate includes a center element and plurality of radial elements extending from a center hub. In the operative mode, the radial elements are folded upwardly into an approximately vertical position, with the center element at the center of the hub and the radial elements circumferentially surrounding the center element. In one embodiment the center element serves an active element of the antenna array and the radial elements are controllable in a directive or reflective state to effect a directive beam pattern from the antenna array. When not in use, the antenna elements are deformed into a plane and can therefore be integrated into a housing for compact storage. In a phased array embodiment, the center element is absent and the plurality of radial elements, are controllable to steer the antenna beam.

Abstract: A security system that protects an apparatus from (e.g. theft) comprises at least one secured apparatus having an identification code, an operation center having a memory with the identification code of the secured apparatus stored in association with an operation-permitting code and a gateway apparatus connecting the secured apparatus and the operation center. The gateway apparatus and the operation center are connected via a permanently connectable line, which is not subject to connection time charges. When the secured apparatus is turned on, the secured apparatus transmits the identification code to the operation center via the line. Then, the operation center searches the table for an operation-permitting code corresponding to the identification code, and transmits the operation-permitting code retrieved from the memory to the secured apparatus via the line, if the operation-permitting code corresponding to the identification code is found.

Abstract: The present invention enables control to be prioritized based on data content over a network such as the Internet. In the present invention, a data sending unit adds metadata relating to data content upon data, decides priority of resources based on metadata while referring to a metapolicy, generates a packet, and sets priority at a part of the header information of the packet. A data transmission unit then refers to a DSCP table and then transmits or discards the packet based on communication control based on priority set at the packet.

Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

Abstract: A driver assist information providing system 1, which includes a driver assist information transmitter 2 and a driver assist information receiver 3.

Abstract: A network element management system which automatically configures itself, when an operator enters a component identifier, for optimal full-featured management of the identified component. This is preferably done by an autodiscovery process, and not by any mere lookup.

Abstract: Disclosed is a system which provides virtual Ethernet and virtual Wireless Ethernet (e.g. 802.11b) interfaces for client using a single host device. Providing virtual Ethernet interfaces for a client requires one physical Ethernet card/interface. Providing virtual Wireless Ethernet interfaces for a client requires two physical wireless Ethernet cards/interfaces. Applications can use these virtual interfaces as if they are real interfaces using socket interfaces.

Abstract: A parallel monitored and controlled optical PMD compensator comprises a branch optical signal split from an optical signal path. A polarization controller (PC) and differential group delay are disposed in each of the paths. A controller adjusts polarization compensation of the PCs in response to PMD dispersion of the branch optical signal. A PMD monitor is preferably disposed in the branch path providing a monitor signal to the controller for use in adjusting the PCs. A polarization rotator may inject a reference signal into the paths with the PC disposed in the branch path acting as a polarization scrambler. A state of polarization (SOP) of the reference signal may be monitored by polarimeters disposed in both paths and the SOP of the reference signal in the branch path may be provided to the controller for adjusting polarization compensation of the inline PC.

Abstract: A link level flow control technique implements a “pull frame” transmission model in a Fibre Channel network. In one embodiment, frames remain in a first Fibre Channel device until they are requested by a second Fibre Channel device, wherein the second Fibre Channel device does not issue a request unless conditions are such that it can immediately transmit the frame toward its target destination. In another embodiment, a Fibre Channel device provides hardware messaging capability to support the pull model. In yet another embodiment, multiple Fibre Channel devices in accordance with the invention may be coupled to provide high port-count Fibre Channel switches.

Abstract: A method and system for constructing orthogonal codes of length N for use in a network utilizing quasi-synchronous code division multiple access combined with time division duplexing. The method determines the balanced vectors of length N, being all possible cross-correlation vectors resulting from zero cross-correlation of codes of length N. An arbitrary code of length N is utilized, and a bitwise XOR-ing is performed with all the balanced vectors to produce a set of codes with which the arbitrary code is orthogonal. A bitwise XOR-ing of the original balanced vectors is performed and the code is added to a set of orthogonal codes if the result of the bitwise XOR-ing of the original balanced vectors is balanced. The method is repeated until the set of orthogonal codes is complete.

Abstract: The capacitor component is mounted on a component assembly carrier provided with electronic circuit elements. The capacitor component includes at least two capacitors (C1, C2) formed on a common dielectric substrate plate (1). To avoid production-caused fluctuations in the capacitances in the production of identical kinds of capacitors with the same capacitances, first and third electrode layers for the capacitors (C1, C2) are applied at the same time to the top side of the dielectric substrate plate, and the second and fourth electrode layers are applied at the same time to the underside of the dielectric substrate plate opposite to the first and third dielectric layers respectively. The spatial dimensions of the third electrode layer correspond to the dimensions of the first electrode layer, and the spatial dimensions of the fourth electrode layer correspond to the dimensions of the second electrode layer, so that the respective capacitances of the capacitors (C1, C2) are matched as precisely as possible.

Abstract: A communication hub for providing continuity testing in communication networks. The communication hub comprises a processor coupled to an interface. The processor is configured to process a continuity test instruction to generate a request for continuity acknowledgment message. The interface is configured to receive the continuity test instruction and transmit the request for continuity acknowledgment message.

Abstract: The present invention provides a network device, such as a network switch or a router, having a high degree of modularity and reliability. The network device includes a data plane and a control plane. The data plane relays datagrams between a pair of receive and transmit network interface ports. The control plane runs management and control operations, such as routing and policing algorithms which provide the data plane with instructions on how to relay cell/packets/frames. Further, the control plane includes an internal control device that is primarily responsible for managing the internal resources of the network device, and a separate external control device that is primarily responsible for operations relating to the interfacing of the network device with an external environment.

Abstract: An improvement of an ATM transmission system between a mobileservices switching center and a base station in a mobile communication system. A delay time for generating/sending out a cell is minimized to ensure the information quality required for real time transmission. When the transmission interval of a call type a is T, call types b and c whose periods are twice and four time that of the call type a should be transmitted at intervals twice and four times that of the call type a. A transmitted frame assembler/disassembler 104 in the base station prepares transmitted frames 201 each including the cell slots 201-1, 201-2 and 201-3 for transferring the respective call types, and schedules such that the transmitted frames are sent out to a channel 112 at the interval T, thereby enabling the transmission to be carried out without delay.

Abstract: The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known reference clock for a digital signal processor. A first counter counts the reference clock cycles during the same time period in which a second counter counts the processor clock cycles. The number of processor clock cycles counted is divided by the number of reference clock cycles counted and the result is multiplied by the frequency of the reference clock. The calculated processor clock frequency is compared to a table of available CPU clock speeds and the closest available clock speed is selected. The selected available clock speed is then stored as a variable in RAM for use by all software which uses the processor clock as a base for generating absolute timing signals, such as a one second clock.