Abstract: A symmetric, multi-layer, three-way power divider that is equally balanced, with resistors placed between all combinations of legs. This three-way power divider is specifically designed to be used in millimeter wave applications (e.g., 5G in the 20 GHz-40 GHz range for both dual and single polarization), specifically in designs where a common signal is distributed to a multiple of three elements. This three-way power divider also can be useful for addressing space constraints in 5G applications, e.g., due to routing limitations.

Abstract: A selective calibration system for signal processing integrated circuits includes a calibration information generator that receives information identifying a group of signal processing integrated circuits associated with a product, the group of signal processing integrated circuits being a subset of a population of signal processing integrated circuits for which performance information is stored, and uses the performance information to produce calibration information for the identified signal processing integrated circuits as a group. The calibration information generator generally uses only performance information associated with the identified signal processing integrated circuits to produce the calibration information so that each signal processing integrated circuit in the group is calibrated relative to just that group of signal processing integrated circuits. Direct product access to the calibration information generator can be provided.

Abstract: A phased array includes a laminar substrate having both 1) a plurality of elements forming a patch phased array, and 2) a plurality of integrated circuits. Each integrated circuit is configured to control receipt and transmission of signals by the plurality of elements in the patch phased array. The integrated circuits also are configured to operate the phased array at one or more satellite frequencies—to transmit signals to and/or receive signals from a satellite. Each integrated circuit physically couples with one corresponding element so that incoming signals are received by the corresponding element in a first polarization, and outgoing signals are transmitted by the corresponding element in a second polarization. The phased array isolates the transmit signals from the receive signals by orienting the first and second polarizations differently.

Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.

Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Abstract: This patent application describes systems, devices, and methods for element-level self-calculation of phased array vectors by a beam forming ASIC using direct calculation such as for fast beam steering.

Abstract: A phased antenna array system is provided that includes a beamforming integrated circuit and beamforming elements in communication with the integrated circuit disposed on a substrate. The beamforming integrated circuit includes multiple radio frequency (RF) signal ports. One or more of the RF signal ports includes an RF signal pad disposed between an edge of the integrated circuit and an internal RF ground pad. The RF signal pad and the internal RF ground pad of the RF signal port are oriented perpendicular with respect to the edge of the integrated circuit. Specifically, the RF signal pad has a first side disposed on or adjacent to the edge of the integrated circuit and an opposing second side that is adjacent to the internal RF ground pad. A method of controlling the phased antenna array system is also provided.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: An envelope stacking power amplifier system reduces current for a given output power level without sacrificing the ability to support large voltage swings at saturation and therefore increases efficiency at the maximum linear operating power and all power levels below that. The system includes a stack/unstack controller including circuitry configured to switch the RF power amplifier system between a stacked mode in which first and second RF amplifiers are coupled in a stacked configuration and an unstacked mode in which the first and second RF amplifiers are coupled in an unstacked configuration in response to one or more mode-control signals, the stacked configuration providing reduced current compared to the unstacked configuration.

Abstract: Exemplary embodiments dynamically select the LO frequency and mixer mode (i.e., low-side LO injection or high-side LO injection) for upconversion based on the desired RF output frequency in order to mitigate the effects of spurious and LO leakage signals that could violate radiation emission limits, e.g., in the case where the IF signal frequency is smaller than the RF operating band. By dynamically switching the LO frequency and mixer mode as a function of the requested operating RF channel, low-level emissions and spurious signal compliance with restricted bands can be achieved.

Abstract: A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.

Abstract: A beamforming integrated circuit system is configured to optimize performance. Among other things, the system may run at a lower power than conventional integrated circuits, selectively disable branches to control certain system functions, and/or selectively position ground pads around receiving pads to enhance isolation. The system also may use a beamforming integrated circuit as a distribution circuit for a number of similar or like beamforming integrated circuits.

Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Abstract: A phased array includes a laminar substrate having both 1) a plurality of elements forming a patch phased array, and 2) a plurality of integrated circuits. Each integrated circuit is configured to control receipt and transmission of signals by the plurality of elements in the patch phased array. The integrated circuits also are configured to operate the phased array at one or more satellite frequencies—to transmit signals to and/or receive signals from a satellite. Each integrated circuit physically couples with one corresponding element so that incoming signals are received by the corresponding element in a first polarization, and outgoing signals are transmitted by the corresponding element in a second polarization. The phased array isolates the transmit signals from the receive signals by orienting the first and second polarizations differently.

Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.

Abstract: This patent application describes systems, devices, and methods for element-level self-calculation of phased array vectors by a beam forming ASIC using interpolation and a look-up table for calculation of phase setting values such as for fast beam steering.

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n?1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.

Abstract: An integrated circuit system has a die with first and second sides, and contains high frequency circuitry operating at mm-wave frequencies. The system also has a plurality of interfaces (on the first side) in electrical communication with the high frequency circuitry, and a heat sink having a bottom surface with a first region and an aperture region. The first region is in physical and conductive contact with the die, while the aperture region forms a concavity with an inner concave surface that is spaced from the die.