Patents Assigned to Applied Material Inc.
  • Patent number: 6392333
    Abstract: An enhanced electron source in most respects similar to a standard cathode assembly for an electron gun includes an electron emitter surrounded by a suppressor electrode, the emitted electrons passing through an extractor electrode. Additionally, the suppressor electrode includes a small ring shaped permanent magnet surrounding the opening in the suppressor electrode through which the emitter tip protrudes. The resulting magnetic field is aligned with the beam axis, and includes a tail which forms a very short focal length magnetic lens immediately following the emitter tip. This magnetic field collimates the electron beam before it enters the downstream electrostatic gun lens, thus increasing the effective angular intensity of the cathode assembly. The aberrations of this collimating lens are very low so that its useful brightness is not reduced. Also the influence of guns lens aberrations is reduced because a smaller aperture angle in the gun lens may be used to obtain higher beam current.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Lee H. Veneklasen, William J. DeVore, Rudy F. Garcia
  • Patent number: 6392229
    Abstract: A photolithographic track system for semiconductor wafer manufacture, that includes an Atomic Force Microscope (AFM), having a scanning stylus probe measurement device coupled to the AFM head, for measuring overlay between masks and layers in an inspected wafer, so as to generate overlay data. The AFM is situated in-track.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Stephane Dana, Joseph Bach
  • Patent number: 6391771
    Abstract: The present invention provides Cu lines which are enclosed within Cu diffusion barrier layers, for IC structures such as semiconductor devices. The Cu lines (310) have conventional top (316) and bottom (318) Cu diffusion barrier layers and novel sidewall layers (324 and 326) comprising Cu diffusion barrier materials. The present invention also provides for conductive interconnect lines for semiconductor devices which compensate partly or completely for a misalignment between the line etch pattern and the underlying contact element, such as a via plug. The misalignment tolerant line (430) is formed by fabricating novel sidewalls (438 and 440) on the line wherein the sidewalls have a thickness which equals or exceeds the width of the gap (431) which is caused by the misalignment. The misalignment tolerant line compensates for the misalignment gap and thereby prevents etching a trench in the contact element.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Mehul B. Naik, Suketu A. Parikh
  • Patent number: 6391171
    Abstract: A flangeless feed through supplies power to a device through a passage in a wall of a vacuum chamber. The feed through includes an insulator ring securely positioned in the passage, a first threaded insert, and a second threaded insert which engages the first threaded insert, wherein the insulator ring is gripped by the first and second threaded inserts. The feed through is installed by securely positioning the insulator ring within the passage, inserting the first threaded insert into the passage, and then connecting the first and second threaded inserts to grip the insulator ring.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Timothy C. Lommasson
  • Patent number: 6391163
    Abstract: The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing process in order to improve conductive member and film qualities. The copper may be alloyed with magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Vikram Pavate, Murali Abburi, Murali Narasimhan, Seshadri Ramaswami
  • Patent number: 6390908
    Abstract: Apparatus and methods of polishing substrates are disclosed. A retaining ring for a polishing apparatus includes an inner surface exposed to contact a peripheral edge of a substrate to be polished against a polishing surface, a bottom surface exposed to contact the polishing surface while the substrate is being polished, and a wear marker indicative of a preselected amount of wear of the bottom surface. The inner surface, bottom surface and wear marker may form part of a retaining ring used in chemical mechanical polishing operations. In one method, one or more substrates may be polished against a polishing surface using the retaining ring, and at least a portion of the retainer may be replaced when the bottom surface has been worn away by the preselected amount indicated by the wear marker.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Hung Chih Chen, Steven M. Zuniga, Bret W. Adams, Manoocher Birang, Kean Chew
  • Patent number: 6391776
    Abstract: A method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. Using a contact via as an example of a high aspect ratio feature, we have demonstrated that it is possible to increase the copper seed layer coverage simultaneously at both the bottom of the via and on the wall of the via . This increase is achieved by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. For features having a 0.25 &mgr;m or smaller feature size, an aspect ratio of about 3:1 requires that about 50% or more of the copper species be ions at the time of deposition on the substrate.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Imran Hashim, Hong-Mei Zhang, John C. Forster
  • Patent number: 6391790
    Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Brigitte C. Stoehr, Michael D. Welch
  • Patent number: 6390904
    Abstract: The present invention provides a retaining ring having an resilient liner for protecting the substrate edge from being damaged during chemical mechanical polishing and a method for making the same. Retainers made of wear resistant ceramics, such as alumina, provide better overall performance, including wear resistance, and reduced particle formation than other retaining ring materials. By incorporating a resilient liner, such as an epoxy, on the inner surface of the wear resistant ring, the substrate edge is protected from damage that can be easily caused by the hard surface of the ceramic alone.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Allan Gleason, Manoocher Birang, John Prince, Mohsen Salek, Syed Askari
  • Patent number: 6390019
    Abstract: A process chamber 35 for processing a substrate 30 and monitoring the process conducted on the substrate 30, comprises a support 45, a gas distributor, and an exhaust 85. The process chamber 35 has a wall comprising a window 130 that allows light to be transmitted therethrough and reduces deposition of process residue from the process gas onto the window 130 during processing of the substrate 30. In one version, the window 130 comprises a transparent plate 135 covered by an overlying mask 140 that has at least one aperture 145 extending through the mask 140 so that light can be transmitted through the aperture 145 and the transparent plate 135.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Michael N. Grimbergen, Xue-Yu Qian
  • Patent number: 6391788
    Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
  • Publication number: 20020058408
    Abstract: The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.
    Type: Application
    Filed: January 10, 2002
    Publication date: May 16, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Dan Maydan, Ashok K. Sinha, Zheng Xu, Liang-Yuh Chen, Roderick Craig Mosely, Daniel Carl, Diana Xiaobing Ma, Yan Ye, Wen Chiang Tu
  • Publication number: 20020057427
    Abstract: A method and apparatus for reducing speckle during inspection of articles used in the manufacture of semiconductor devices, including wafers, masks, photomasks, and reticles. The coherence of a light beam output by a coherent light source, such as a pulsed laser, is reduced by disposing elements in a light path. Examples of such elements include optical fiber bundles; optical light guides; optical gratings; an integrating sphere; and an acousto-optic modulator. These various elements may be combined as desired, such that light beams output by the element combinations have optical path length differences that are greater than a coherence length of the light beam output by the coherent light source.
    Type: Application
    Filed: January 11, 2002
    Publication date: May 16, 2002
    Applicant: APPLIED MATERIALS, INC
    Inventors: Avner Karpol, Silviu Reinhorn, Emanuel Elysaf, Shimon Yalov, Boaz Kenan
  • Patent number: 6387761
    Abstract: A method for improving the interface between a silicon nitride film and a silicon surface is described. According to the present invention a silicon nitride film is formed on a silicon surface of a substrate. While said substrate is heated the silicon nitride film is exposed to an ambient comprising hydrogen (H2). In a prefered embodiment of the present invention the ambient comprises H2 and N2.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: May 14, 2002
    Assignees: Applied Materials, Inc., Vanguard Semiconductor, Ltd.
    Inventors: Wong-Cheng Shih, Pravin K. Narwankar, Randall S. Urdahl, Turgut Sahin
  • Patent number: 6386947
    Abstract: A method and apparatus for detecting the disengagement of a workpiece from a polishing head is provided. In one embodiment, the apparatus generally includes a polishing head and a detector. The polishing head has a fixed portion and a first portion. The detector is adapted to provide a metric indicative of relative motion between the fixed portion and the first portion.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Timothy J. Donohue
  • Patent number: 6387819
    Abstract: A method of etching an organic dielectric layer 10 on a substrate 15 with a high etching rate and a high etching selectivity ratio. The organic dielectric layer 10 comprises a low k dielectric material, such as a silicon-containing organic polymer, for example, benzocyclobutene. A patterned mask layer is formed on the organic dielectric layer 10, and the substrate 15 is placed in a process zone 35 of a process chamber 30. An energized process gas introduced into the process zone 35, comprises an oxygen-containing gas for etching the organic dielectric layer 10, a non-reactive gas for removing dissociated material to enhance the etching rate, and optionally, passivating gas for forming passivating deposits on sidewalls 90 of freshly etched features to promote anisotropic etching. Preferably, during etching, the temperature of substrate 15 is maintained at a low temperature of from about 15° C. of 80° C. to enhance the rate of etching of the dielectric layer.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Min Yu
  • Patent number: 6387288
    Abstract: An apparatus and method for scavenging etchant species from a plasma formed of etchant gas prior to the etchant gas entering a primary processing chamber of a plasma reactor. There is at least one scavenging chamber, each of which is connected at an inlet thereof to an etchant gas source and at an outlet thereof to a gas distribution device of the primary processing chamber. Each scavenging chamber has a radiation applicator that irradiates the interior of the scavenging chamber and creates a plasma therein from etchant gas flowing through the chamber from the etchant gas source to the gas distribution apparatus of the primary processing chamber. The applicator uses either an inductive discharge, capacitive discharge, direct current (DC) discharge or microwave discharge to irradiate the interior of the scavenging chamber and ignite the plasma. An etchant species scavenging source is also disposed within the scavenging chamber.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Claes Bjorkman, Hongching Shan, Michael Welch
  • Patent number: 6386963
    Abstract: The present invention generally provides an apparatus and a method for conditioning a polishing pad in a polishing system. In one embodiment, the apparatus includes a conditioning disk having conditioning elements disposed on the bottom surface and away from the center portion of the disk. In another embodiment, the apparatus includes a base plate and a ring-shaped plate in which the conditioning elements are disposed on the ring-shaped plate. In still another embodiment, the apparatus includes a conditioning disk having conditioning elements disposed on the bottom surface and away from the center portion of the disk and having brush bristles disposed on the center portion of the disk.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Suzuki Kenji, Raijiro Koga
  • Patent number: 6387207
    Abstract: A compact, self-contained remote plasma generator is mounted on the lid of a semiconductor processing chamber to form an integrated substrate processing system. The remote plasma generator is activated in a clean operation to generate cleaning plasma species to provide better cleaning of the chamber and lower perfluorocarbon emissions than in situ plasma clean processes. A three-way valve is adjustable to control gas flow to the chamber. During the clean operation, the three-way valve directs a cleaning plasma precursor from a first gas line to the remote plasma generator to generate cleaning plasma species which are flowed to the chamber for cleaning deposits therein. During a deposition process, the three-way valve directs a first process gas from the flat gas line to the chamber, bypassing the remote plasma generator.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Karthik Janakiraman, Kelly Fong, Chen-An Chen, Paul Le, Rong Pan, Shankar Venkataraman
  • Patent number: 6386955
    Abstract: A carrier head for a chemical mechanical polishing apparatus. The carrier head includes a housing, a base, a loading mechanism, a gimbal mechanism, and a substrate backing assembly. The substrate backing assembly includes a support structure positioned below the base, a substantially horizontal, annular flexure connecting the support structure to the base, and a flexible membrane connected to the support structure. The flexible membrane has a mounting surface for a substrate, and extends beneath the base to define a chamber.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: May 14, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Steven M. Zuniga, Manoocher Birang, Hung Chen, Sen-Hou Ko