Patents Assigned to Applied Material
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Publication number: 20210336134Abstract: A crested barrier memory and selector device may include a first electrode, a first self-rectifying, tunneling layer having a first dielectric constant, and an active, barrier layer that has a second dielectric constant and another self-rectifying, tunneling layer having a third dielectric constant. The first self-rectifying layer may be between the first electrode and the active layer. The second dielectric constant may be at least 1.5 times larger than the first dielectric constant. The device may also include a second electrode, where the active, barrier layer is between the first self-rectifying, tunneling layer and the second electrode.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Applicant: Applied Materials, Inc.Inventor: Milan Pe{hacek over (s)}ic
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Publication number: 20210333703Abstract: Extreme ultraviolet (EUV) mask blanks and methods for their manufacture, and production systems therefor are disclosed. The method for forming an EUV mask blank comprises smoothing out surface defects on a surface of a substrate.Type: ApplicationFiled: April 20, 2021Publication date: October 28, 2021Applicant: Applied Materials, IncInventors: Wen Xiao, Vibhu Jindal, Weimin Li, Sanjay Bhat, Azeddine Zerrade
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Publication number: 20210335574Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a plurality of recesses extending about and radially outward of the plurality of apertures.Type: ApplicationFiled: April 23, 2020Publication date: October 28, 2021Applicant: Applied Materials, Inc.Inventors: Fang Ruan, Prashant Kumar Kulshreshtha, Rajaram Narayanan, Diwakar Kedlaya
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Publication number: 20210335635Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body along a first surface of the first lid plate. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of apertures of the plurality of apertures. The plurality of lid stacks may at least partially define a plurality of processing regions vertically offset from the transfer region. The systems may include a second lid plate coupled with the plurality of lid stacks. The plurality of lid stacks may be positioned between the first lid plate and the second lid plate. A component of each lid stack of the plurality of lid stacks may be coupled with the second lid plate.Type: ApplicationFiled: April 23, 2020Publication date: October 28, 2021Applicant: Applied Materials, Inc.Inventor: Viren Kalsekar
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Patent number: 11158540Abstract: Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.Type: GrantFiled: May 26, 2017Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Wenguang Li, James S. Papanu, Wei-Sheng Lei, Prabhat Kumar, Brad Eaton, Ajay Kumar, Alexander N. Lerner
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Patent number: 11154935Abstract: An additive manufacturing apparatus includes a platform, a dispenser configured to deliver a plurality of successive layers of feed material on the platform, at least one energy source to selectively fuse feed material in a layer on the platform, and an air knife supply unit. The air knife supply unit includes a tube having a plurality of holes spaced along a length of the tube, a multi-fluted helical screw positioned in the tube, a gas inlet configured to supply a gas into an end of the tube with the screw configured to guide the gas from the gas inlet through the tube and out the holes, and a spiral plenum surrounding the tube with the spiral plenum including an inner end to receive gas from the holes and an outer end to deliver the gas over the platform.Type: GrantFiled: May 31, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Bahubali S. Upadhye, Sumedh Acharya, Sandip Desai, David Masayuki Ishikawa, Eric Ng, Hou T. Ng
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Patent number: 11158524Abstract: A cleaning module for cleaning a wafer comprises a wafer gripping device configured to support a wafer in a vertical orientation and comprises a catch cup and a gripper assembly. The catch cup comprises a wall that has an annular inner surface that defines a processing region and has an angled portion that is symmetric about a central axis of the wafer gripping device. The gripper assembly comprises a first plate assembly, a second plate assembly, a plurality of gripping pin, and a plurality of loading pin. The gripping pins are configured to grip a wafer during a cleaning process and the loading pins are configured to grip the wafer during a loading and unloading process. The cleaning module further comprises a sweep arm coupled to a nozzle mechanism configured to deliver liquids to the front and back side of the wafer.Type: GrantFiled: August 6, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Jagan Rangarajan, Adrian Blank, Edward Golubovsky, Balasubramaniam Coimbatore Jaganathan, Steven M. Zuniga, Ekaterina Mikhaylichenko, Michael A. Anderson, Jonathan P. Domin
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Patent number: 11154961Abstract: A method of fabricating a polishing pad using an additive manufacturing system includes receiving data indicative of a desired shape of the polishing pad to be fabricated by droplet ejection. The desired shape defines a profile including a polishing surface and one or more grooves on the polishing pad. Data indicative of a modified pattern of dispensing feed material is generated to at least partially compensate for distortions of the profile caused by the additive manufacturing system, and a plurality of layers of the feed material are dispensed by droplet ejection in accordance to the modified pattern.Type: GrantFiled: January 8, 2020Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Mayu Felicia Yamamura, Jason Garcheung Fung, Daniel Redfield, Rajeev Bajaj, Hou T. Ng
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Patent number: 11157661Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.Type: GrantFiled: December 16, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Vinayak Veer Vats, Sidharth Bhatia, Garrett Ho-Yee Sin, Pramod Nambiar, Hang Yu, Sanjay Kamath, Deenesh Padhi, Heng-Cheng Pai
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Patent number: 11156566Abstract: Methods for performing imaging reflectometry measurements include illuminating a measurement area on a sample using an input beam having a first peak wavelength, and obtaining multiple images of the measurement area using portions of the input beam reflected from the sample. A reflectance intensity value is determined for each of a plurality of pixels in each of the images. A parameter associated with the particular structure is determined using the reflectance intensity value.Type: GrantFiled: March 26, 2020Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Guoheng Zhao, Mehdi Vaez-Iravani
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Patent number: 11158791Abstract: A selector device for a memory cell in a memory array includes a first electrode, a second electrode, and a separator between the first electrode and the second electrode. The separator includes a mixed ionic-electronic conduction material with first ions having a first charge such that the first ions respond to a voltage applied between the first electrode and the second electrode by moving away from the first electrode. The separator is doped near the second electrode with second ions having a second charge that opposes the first charge.Type: GrantFiled: November 21, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Milan Pe{hacek over (s)}ic, Andrea Padovani, Bastien Beltrando
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Patent number: 11158528Abstract: Methods and systems for controlling temperatures in plasma processing chamber with a combination of proportional and pulsed fluid control valves. A heat transfer fluid loop is thermally coupled to a chamber component, such as a chuck. The heat transfer fluid loop includes a supply line and a return line to each of hot and cold fluid reservoirs. In an embodiment, an analog valve (e.g., in the supply line) is controlled between any of a closed state, a partially open state, and a fully open state based on a temperature control loop while a digital valve (e.g., in the return line) is controlled to either a closed state and a fully open state.Type: GrantFiled: February 22, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventor: Chetan Mahadeswaraswamy
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Patent number: 11158650Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.Type: GrantFiled: October 18, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: ChangSeok Kang, Tomohiko Kitajima
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Patent number: 11159159Abstract: A method of controlling a headroom voltage of a transistor stage of an electroplating system to maintain a target power dissipation across the transistor stage may include maintaining a headroom voltage in the transistor stage for a load in the electroplating system. The method may also include measuring an instantaneous power dissipation in the transistor stage and generating a difference output representing a difference between the instantaneous power dissipation in the transistor stage and the target power dissipation in the transistor stage. A voltage across the transistor stage and the load may then be adjusted using the difference output such that the headroom voltage in the transistor stage is adjusted to maintain the target power dissipation in the transistor stage.Type: GrantFiled: September 9, 2020Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventor: Mikael R. Borjesson
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Patent number: 11158526Abstract: Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heater assembly. The substrate support assembly comprises an upper surface and a lower surface; one or more main resistive heaters disposed in the substrate support; and a plurality of heaters in column with the main resistive heaters and disposed in the substrate support. A quantity of the heaters is an order of magnitude greater than a quantity of the main resistive heaters and the heaters are independently controllable relative to each other as well as the main resistive heater.Type: GrantFiled: May 22, 2014Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: Vijay D. Parkhe, Konstantin Makhratchev, Masanori Ono, Zhiqiang Guo
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Patent number: 11158527Abstract: A workpiece holder includes a puck having a cylindrical axis, a radius about the cylindrical axis, and a thickness. At least a top surface of the puck is substantially planar, and the puck defines one or more thermal breaks. Each thermal break is a radial recess that intersects at least one of the top surface and a bottom surface of the cylindrical puck. The radial recess has a thermal break depth that extends through at least half of the puck thickness, and a thermal break radius that is at least one-half of the puck radius. A method of processing a wafer includes processing the wafer with a first process that provides a first center-to-edge process variation, and subsequently, processing the wafer with a second process that provides a second center-to-edge process variation that substantially compensates for the first center-to-edge process variation.Type: GrantFiled: November 4, 2019Date of Patent: October 26, 2021Assignee: Applied Materials, Inc.Inventors: David Benjaminson, Dmitry Lubomirsky
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Microwave Plasma Source For Spatial Plasma Enhanced Atomic Layer Deposition (PE-ALD) Processing Tool
Publication number: 20210327686Abstract: Plasma source assemblies, gas distribution assemblies including the plasma source assembly and methods of generating a plasma are described. The plasma source assemblies include a powered electrode with a ground electrode adjacent a first side and a dielectric adjacent a second side. A first microwave generator is electrically coupled to the first end of the powered electrode through a first feed and a second microwave generator is electrically coupled to the second end of the powered electrode through a second feed.Type: ApplicationFiled: April 29, 2021Publication date: October 21, 2021Applicant: Applied Materials, Inc.Inventors: Xiaopu Li, Jozef Kudela, Kallol Bera, Tsutomu Tanaka, Dmitry A. Dzilno -
Publication number: 20210327717Abstract: Methods and apparatus for the formation of cobalt disilicide are described. Some embodiments of the disclosure provide in-situ methods of forming cobalt disilicide. The resulting films are smoother and have lower resistance and resistivity than films formed by similar ex-situ methods. Some embodiments of the disclosure provide apparatus for performing the described methods without an air break between processes.Type: ApplicationFiled: April 15, 2020Publication date: October 21, 2021Applicant: Applied Materials, Inc.Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Kazuya Daito
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Publication number: 20210325777Abstract: Embodiments of the present disclosure generally relate to optically densified nanoimprint films and processes for making these optically densified nanoimprint films, as well as optical devices containing the optically densified nanoimprint films. In one or more embodiments, a method of forming a nanoimprint film includes positioning a substrate containing a porous nanoimprint film within a processing chamber, where the porous nanoimprint film contains nanoparticles and voids between the nanoparticles, and the porous nanoimprint film has a refractive index of less than 2. The method also includes depositing a metal oxide on the porous nanoimprint film and within at least a portion of the voids to produce an optically densified nanoimprint film during an atomic layer deposition (ALD) process.Type: ApplicationFiled: December 29, 2020Publication date: October 21, 2021Applicant: Applied Materials, Inc.Inventors: Andrew CEBALLOS, Rami HOURANI, Kenichi OHNO, Yuriy MELNIK, Amita JOSHI
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Publication number: 20210327752Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high quality gapfill. Some embodiments utilize chemical vapor deposition, plasma vapor deposition, physical vapor deposition and combinations thereof to deposit the gapfill. The gapfill is of high quality and similar in properties to similarly composed bulk materials.Type: ApplicationFiled: June 29, 2021Publication date: October 21, 2021Applicant: Applied Materials, Inc.Inventors: Samuel E. Gottheim, Eswaranand Venkatasubramanian, Pramit Manna, Abhijit Basu Mallick
