Patents Assigned to Applied Material
  • Publication number: 20210325771
    Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from carbon and antimony.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 21, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Shuwei Liu, Vibhu Jindal
  • Publication number: 20210327891
    Abstract: Memory devices and methods of manufacturing memory devices are provided. A plasma enhanced chemical vapor deposition (PECVD) method to form a memory cell film stack having more than 50 layers as an alternative for 3D-NAND cells is described. The memory stack comprises alternating layers of a first material layer and a second material layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: October 21, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick, Huiyuan Wang, Susmit Singha Roy
  • Patent number: 11150078
    Abstract: Methods for performing imaging reflectometry measurements include determining a representative reflectance intensity value using multiple images of a measurement area that includes a particular structure and/or using a plurality of pixels each associated with the particular structure within the measurement area. A parameter associated with the particular structure is determined using the representative reflectance intensity value.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 19, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Guoheng Zhao, Mehdi Vaez-Iravani
  • Patent number: 11152373
    Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One non-limiting method may include providing a device, the device including a plurality of angled structures formed from a substrate, a bitline and a dielectric between each of the plurality of angled structures, and a drain disposed along each of the plurality of angled structures. The method may further include providing a plurality of mask structures of a patterned masking layer over the plurality of angled structures, the plurality of mask structures being oriented perpendicular to the plurality of angled structures. The method may further include etching the device at a non-zero angle to form a plurality of pillar structures.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: October 19, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Sony Varghese
  • Patent number: 11152248
    Abstract: Embodiments disclosed herein relate to cluster tools for forming and filling trenches in a substrate with a flowable dielectric material. In one or more embodiments, a cluster tool for processing a substrate contains a load lock chamber, a first vacuum transfer chamber coupled to the load lock chamber, a second vacuum transfer chamber, a cooling station disposed between the first vacuum transfer chamber and the second vacuum transfer chamber, a factory interface coupled to the load lock chamber, a plurality of first processing chambers coupled to the first vacuum transfer chamber, wherein each of the first processing chambers is a deposition chamber capable of performing a flowable layer deposition, and a plurality of second processing chambers coupled to the second vacuum transfer chamber, wherein each of the second processing chambers is a plasma chamber capable of performing a plasma curing process.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 19, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Yong Sun, Jinrui Guo, Praket P. Jha, Jung Chan Lee, Tza-Jing Gung, Mukund Srinivasan
  • Patent number: 11151710
    Abstract: There is provided a system comprising a processor configured to obtain a set of images of a semiconductor specimen, (1) for an image of the set of images, select at least one algorithmic module MS out of a plurality of algorithmic modules, (2) feed the image to MS to obtain data DMS representative of one or more defects in the image, (3) obtain a supervised feedback regarding rightness of data DMS, (4) repeat (1) to (3) for a next image until a completion criterion is met, wherein an algorithmic module selected at (1) is different for at least two different images of the set of images, generate, based on the supervised feedback, a score for each of a plurality of the algorithmic modules, and use scores to identify one or more algorithmic modules Mbest as the most adapted for providing data representative of one or more defects in the set of images.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 19, 2021
    Assignee: Applied Materials Israel Ltd.
    Inventors: Ran Schleyen, Eyal Zakkay, Boaz Cohen
  • Publication number: 20210320027
    Abstract: Exemplary methods of semiconductor processing may include coupling a fluid conduit within a substrate support in a semiconductor processing chamber to a system foreline. The coupling may vacuum chuck a substrate with the substrate support. The methods may include flowing a gas into the fluid conduit. The methods may include maintaining a pressure between the substrate and the substrate support at a pressure higher than the pressure at the system foreline.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Zubin Huang, Rui Cheng, Diwakar Kedlaya, Satish Radhakrishnan, Anton V. Baryshnikov, Venkatanarayana Shankaramurthy, Karthik Janakiraman, Paul L. Brillhart, Badri N. Ramamurthi
  • Publication number: 20210317570
    Abstract: Methods for selectively depositing on surfaces are disclosed. Some embodiments of the disclosure utilize an organometallic precursor that is substantially free of halogen and substantially free of oxygen. Deposition is performed to selectively deposit a metal film on a non-metallic surface over a metallic surface. Some embodiments of the disclosure relate to methods of gap filling.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Wei Lei, Sang Ho Yu
  • Publication number: 20210320017
    Abstract: Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports, and each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may include an end effector coupled with the rotatable shaft. The end effector may include a central hub defining a central aperture fluidly coupled with a purge source. The end effector may also include a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Nitin Pathak, Vinay Prabhakar, Badri N. Ramamurthi, Viren Kalsekar, Tuan A. Nguyen, Juan Carlos Rocha-Alvarez
  • Publication number: 20210320018
    Abstract: Exemplary substrate processing systems may include chamber body defining a transfer region. The systems may include a lid plate seated on the chamber body. The lid plate may define a first plurality of apertures through the lid plate and a second plurality of apertures through the lid plate. The systems may include a plurality of lid stacks equal to a number of apertures of the first plurality of apertures defined through the lid plate. Each lid stack of the plurality of lid stacks may include a choke plate seated on the lid plate along a first surface of the choke plate. The choke plate may define a first aperture axially aligned with an associated aperture of the first plurality of apertures. The choke plate may define a second aperture axially aligned with an associated aperture of the second plurality of apertures.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Siva Chandrasekar, Satish Radhakrishnan, Rajath Kumar Lakkenahalli Hiriyannaiah, Viren Kalsekar, Vinay Prabhakar
  • Publication number: 20210317577
    Abstract: Gas distribution assemblies and process chamber comprising gas distribution assemblies are described. The gas distribution assembly includes a gas distribution plate, a lid and a primary O-ring. The primary O-ring is positioned between a purge channel of a first contact surface of the gas distribution plate and a second contact surface. Methods of sealing a process chamber using the disclosed gas distribution assemblies are described.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Muhannad Mustafa, Muhammad M. Rasheed
  • Publication number: 20210319981
    Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and the substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The faceplate may be characterized by a central axis. The faceplate may define a plurality of apertures through the faceplate distributed in a number of rings. Each ring of apertures may include a scaled increase in aperture number from a ring radially inward. A radially outermost ring of apertures may be characterized by a number of apertures reduced from the scaled increase in aperture number.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Arun Thottappayil, Mayur Govind Kulkarni, Junghoon Sun, Jun Tae Choi, Hang Yu
  • Publication number: 20210317578
    Abstract: Exemplary semiconductor processing chambers may include a substrate support positioned within a processing region of the semiconductor processing chamber. The chamber may include a lid plate. The chamber may include a gasbox positioned between the lid plate and the substrate support. The gasbox may be characterized by a first surface and a second surface opposite the first surface. The gasbox may define a central aperture. The gasbox may define an annular channel in the first surface of the gasbox extending about the central aperture through the gasbox. The gasbox may include an annular cover extending across the annular channel defined in the first surface of the gasbox. The chamber may include a blocker plate positioned between the gasbox and the substrate support. The chamber may include a ferrite block positioned between the lid plate and the blocker plate.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Shuran Sheng, Lin Zhang, Joseph C. Werner
  • Publication number: 20210320106
    Abstract: Memory devices and methods of forming memory devices are described. Specifically, dynamic random-access memory (DRAM) devices are provided with a capacitor landing pad able to connect a 6f2 layout to a 4f2 layout. In some embodiments, the capacitor landing pad has a plurality of air gaps.
    Type: Application
    Filed: March 23, 2021
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventor: Russell Chin Yee Teo
  • Publication number: 20210320023
    Abstract: Exemplary substrate support assemblies may include an electrostatic chuck body defining a substrate support surface. The support assemblies may include a support stem coupled with the electrostatic chuck body. The support assemblies may include an electrode embedded within the electrostatic chuck body proximate the substrate support surface. The support assemblies may include a ground electrode embedded within the electrostatic chuck body. The support assemblies may include one or more channels formed within the electrostatic chuck body between the electrode and the ground electrode.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Applied Materials, Inc.
    Inventor: Vijay D. Parkhe
  • Patent number: 11145509
    Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Rui Cheng, Tejinder Singh, Hidetaka Oshio
  • Patent number: 11145504
    Abstract: A method of forming a film stack with reduced defects is provided and includes positioning a substrate on a substrate support within a processing chamber and sequentially depositing polysilicon layers and silicon oxide layers to produce the film stack on the substrate. The method also includes supplying a current of greater than 5 ampere (A) to a plasma profile modulator while generating a deposition plasma within the processing chamber, exposing the substrate to the deposition plasma while depositing the polysilicon layers and the silicon oxide layers, and maintaining the processing chamber at a pressure of greater than 2 Torr to about 100 Torr while depositing the polysilicon layers and the silicon oxide layers.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Jiang, Ganesh Balasubramanian, Arkajit Roy Barman, Hidehiro Kojiri, Xinhai Han, Deenesh Padhi, Chuan Ying Wang, Yue Chen, Daemian Raj Benjamin Raj, Nikhil Sudhindrarao Jorapur, Vu Ngoc Tran Nguyen, Miguel S. Fung, Jose Angelo Olave, Thian Choi Lim
  • Patent number: 11145808
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jong Mun Kim, Minrui Yu, Chando Park, Mang-Mang Ling, Jaesoo Ahn, Chentsau Chris Ying, Srinivas D. Nemani, Mahendra Pakala, Ellie Y. Yieh
  • Patent number: 11145683
    Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Xiangxin Rui, Lai Zhao, Jrjyan Jerry Chen, Soo Young Choi, Yujia Zhai
  • Patent number: 11145761
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim