Abstract: Methods for forming an EUV photoresist hard mask are provided. The method includes treating a metal-rich layer on a substrate with a reductive plasma to form a metallic surface on the metal-rich layer, the metal-rich layer having a top portion comprising a metal oxide layer. The metal-rich layer comprises one or more of tin (Sn), indium (In), gallium (Ga), zinc (Zn), tellurium (Te), antimony (Sb), nickel (Ni), titanium (Ti), aluminum (Al), tantalum (Ta), bismuth (Bi), and lead (Pb).

Abstract: Exemplary semiconductor structures may include a plurality of LED structures and a backplane layer. Exemplary semiconductor structures may also include a light barrier region positioned between the LED structures and the backplane layer. The light barrier region may be operable to absorb light at wavelengths shorter than or about 300 nm and transmit light at wavelengths greater than or about 350.

Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate and on one or more components of the semiconductor processing chamber. The methods may include providing a fluorine-containing precursor to the processing region. The fluorine-containing precursor may be plasma-free when provided to the processing region. The methods may include contacting the silicon-containing material on the one or more components of the semiconductor processing chamber with the fluorine-containing precursor. The methods may include removing at least a portion of the silicon-containing material on the one or more components of the semiconductor processing chamber with the fluorine-containing precursor.

Abstract: Methods for selectively depositing an epitaxial layer are provided. In some implementations, the selective epitaxial deposition process includes providing the co-flow of chlorosilane precursors with at least one of an antimony-containing precursor and a phosphorous-containing precursor. The method utilizes co-flowing of multiple chlorosilane precursors to enable combination of silicon and at least one of phosphorous and antimony in the same matrix using a low-temperature selective process. The deposited epitaxial layer using the epitaxial deposition techniques described not only contains phosphorous and/or antimony but also has a high activated phosphorous and/or antimony concentration.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.

Abstract: Embodiments of the present technology include semiconductor processing methods. The methods may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The methods may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The methods may include forming a doped silicon-containing material on the silicon-containing material. The methods may include oxidizing the substrate. The oxidizing may form an oxidized doped silicon-containing material. The methods may include etching the oxidized doped silicon-containing material.

Abstract: Susceptor assemblies having a susceptor base with a plurality of pockets formed in a surface thereof are described. Each of the pockets has a pocket edge angle in the range of 30 to 75° and a pocket edge radius in the range of 0.40±0.05 mm to 1.20 mm±0.05 mm. The pockets have a raised central region and an outer region that is deeper than the raised central region, relative to the surface of the surface of the susceptor base.

Abstract: Conditions at the perimeter of the wafer may be characterized and used to adjust current stolen by the weir thief electrodes during a plating process to generate more uniform film thicknesses. An electrode may be positioned in a plating chamber near the periphery of the wafer as the wafer rotates. To characterize the electrical contacts on the seal, a wafer with a seed layer may be loaded into the plating chamber, and a constant current may be driven through the electrode into the conductive layer on the wafer. As an electrical characteristic of this current varies, such as a voltage required to drive a constant current, a mapping characterizing the seal quality or the openings in the mask layer may be generated.

Abstract: Exemplary semiconductor processing chamber faceplates may include a body having a first surface and a second surface opposite the first surface. The body may define a plurality of apertures that extend through one or both of the first surface and the second surface. The faceplates may include a heater disposed within an interior of the body. The faceplates may include a first RF mesh disposed between the heater and the first surface. The faceplates may include a second RF mesh disposed between the heater and the second surface. The first RF mesh and the second RF mesh may be coupled together and form a Faraday cage about the heater.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.

Abstract: Exemplary reflective display components are described. These reflective display components may include a microwell layer having a first and a second quantum dot well that each include a plurality of nanoparticles configured to emit a color of light. The microwell layer further has a third well. The reflective display components further include an electrowetting layer positioned above the microwell layer, where the electrowetting layer is operable to independently adjust an intensity of light emitted from the first and second quantum dot wells and the third well in the microwell layer.

Abstract: Embodiments of a showerhead are described herein. In some embodiments, a showerhead assembly includes: a first gas delivery portion having a first body, a first inlet, and a plurality of first tubes extending from the first body and defining a first plenum, wherein each tube of the plurality of first tubes includes a plurality of first holes; and a second gas delivery portion having a second body, a second inlet, and a plurality of second tubes extending from the second body and defining a second plenum fluidly independent from the first plenum, wherein each tube of the plurality of second tubes includes a plurality of second holes, and wherein the plurality of first tubes are disposed in an alternating pattern with the plurality of second tubes across a width of the showerhead assembly and a heat sink disposed between the plurality of first tubes and the plurality of second tubes.

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

Abstract: A vacuum orientation module for a substrate processing system is described. The module includes at least a first vacuum orientation chamber, comprising: a vacuum chamber; a first transportation track within the vacuum chamber, the first transportation track having a first support structure and a first driving structure and defining a transportation direction; an orientation actuator to change the substrate orientation between a non-vertical orientation and a non-horizontal orientation, the vacuum chamber has a first pair of two slit openings, particularly essentially vertical slit openings, at opposing side walls of the vacuum chamber in the transportation direction; and a second transportation track within the vacuum chamber, the second transportation track having a second support structure and a second driving structure extending along the transportation direction, the vacuum chamber has a second pair of two slit openings at the opposing side walls of the vacuum chamber.

Abstract: Controlling a polishing system includes receiving from an in-situ monitoring system, for each region of a plurality of regions on a substrate being processed by the polishing system, a sequence of characterizing values for the region. For each region, a polishing rate is determined for the region, and an adjustment is calculated for at least one processing parameter. For each of a plurality of parameter update times, an adjustment is calculated for at least one processing parameter, wherein calculation of the adjustment for a particular parameter update time from the plurality of parameter update times includes calculation of expected future parameter changes for one or more future parameter update times subsequent to the particular parameter update time.

Abstract: A method and apparatus for manufacturing a flexible layer stack, and to a flexible layer stack. Implementations of the present disclosure particularly relate to a method and apparatus for coating flexible substrates with a low melting temperature metal or metal alloy. In one implementation, a method is provided. The method includes delivering a transfer liquid to a quenching surface of a rotating casting drum. The method further includes forming a material layer stack over the rotating casting drum by delivering a molten metal or molten metal alloy toward the quenching surface of the rotating casting drum. The method further includes transferring the material layer stack from the rotating casting drum to a continuous flexible substrate, wherein the quenching surface of the rotating casting drum is cooled to a temperature at which the layers of the material layer stack solidify.

Abstract: Methods of selectively depositing a carbon-containing layer are described. Exemplary processing methods may include flowing a first precursor over a substrate comprising a metal surface and a non-metal surface to form a first portion of an initial carbon-containing film on the metal surface. The methods may include removing a first precursor effluent from the substrate. A second precursor may then be flowed over the substrate to react with the first portion of the initial carbon-containing layer. The methods may include removing a second precursor effluent from the substrate. The methods may include pre-treating the metal surface of the substrate to form a metal oxide surface on the metal surface.

Abstract: Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

Abstract: A plasma reactor has a cylindrical microwave cavity overlying a workpiece processing chamber, a microwave source having a pair of microwave source outputs, and a pair of respective waveguides. The cavity has first and second input ports in a sidewall and space apart by an azimuthal angle. Each of the waveguides has a microwave input end coupled to a microwave source output and a microwave output end coupled to a respective one of the first and second input ports, a coupling aperture plate at the output end with a rectangular coupling aperture in the coupling aperture plate, and an iris plate between the coupling aperture plate and the microwave input end with a rectangular iris opening in the iris plate.

Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.