Abstract: Light wave separation lattices and methods of formation are provided herein. In some embodiments, a light wave separation lattice includes a first layer having the formula ROXNY, wherein the first layer has a first refractive index; and a second layer, different from the first layer, disposed atop the first layer, and having the formula R?OXNY, wherein the second layer has a second refractive index different from the first refractive index, and wherein R and R? are each one of a metal or a dielectric material. In some embodiments, a method of forming a light wave separation lattice includes depositing a first layer having a predetermined desired refractive index atop a substrate by a physical vapor deposition process; and depositing a second layer, different from the first layer, atop the first layer, wherein the second layer has a predetermined second refractive index different from the first refractive index.

Abstract: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or other silicon-containing materials. The photoexcitation process may expose the substrate and/or gases to an energy beam or flux prior to, during, or subsequent a deposition process. Therefore, the photoexcitation process may be used to pre-treat or post-treat the substrate or material, to deposit the silicon-containing material, and to enhance chamber cleaning processes.

Abstract: A computer-implemented method includes receiving a sequence of current spectra of reflected light from a substrate; comparing each current spectrum from the sequence of current spectra to a plurality of reference spectra from a reference spectra library to generate a sequence of best-match reference spectra; determining a goodness of fit for the sequence of best-match reference spectra; and determining at least one of whether to adjust a polishing rate or an adjustment for the polishing rate, based on the goodness of fit.

Abstract: Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 ? per minute to about 20 ? per minute during the etching process.

Abstract: Methods are provided of fabricating a nitride semiconductor structure. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over one side of the substrate with a thermal chemical-vapor-deposition process. A second layer is similarly deposited over an opposite side of the substrate using the group-III precursor and the nitrogen precursor. The substrate is cooled after depositing the first and second layers without substantially deforming a shape of the substrate.

Abstract: A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.

Abstract: A method of operating a substrate processing chamber comprising transferring a first substrate into the substrate processing chamber and heating the substrate to a first temperature of at least 510° C.; depositing an insulating layer over the first substrate while reducing the temperature of the substrate from the first temperature to a second temperature that is lower than the first temperature; transferring the first substrate out of the substrate processing chamber; removing unwanted deposition material formed on interior surfaces of the chamber during the depositing step by introducing reactive halogen species into the chamber while increasing the temperature of chamber; transferring a second substrate into the substrate processing chamber and heating the substrate to the first temperature; and depositing an insulating layer over the second substrate while reducing the temperature of the substrate from the first temperature to the second temperature.

Abstract: Methods and products, including computer program products, for endpoint determination. An image of a portion of a substrate is captured in-situ, where the image includes optical information that depends on a thickness of a substrate layer. The image is examined to find a location on the substrate, and a process endpoint is determined using a portion of the optical information that corresponds to the location.

Abstract: Methods are provided for depositing a dielectric material. The dielectric material may be used for an anti-reflective coating or as a hardmask. In one aspect, a method is provided for processing a substrate including introducing a processing gas comprising a silane-based compound and an organosilicon compound to the processing chamber and reacting the processing gas to deposit a nitrogen-free dielectric material on the substrate. The dielectric material comprises silicon and oxygen.

Abstract: A chemical mechanical polishing method for polishing an oxide film and a protective film formed on a substrate having recesses comprises four steps. The first step planarizes the oxide film using a polishing pad and a polishing agent containing cerium oxide particles by causing relative rotational motion between the substrate and the polishing pad. The second step continues polishing the oxide film to maintain the planarized property of the oxide film. The third step polishes the oxide film until at least a portion of the protective film becomes exposed. The fourth step polishes the oxide film until the oxide film is substantially removed and the protective film is substantially exposed. During the four steps, torque values are measured on the substrate or the polishing pad, and changes in torque with time are calculated. This information is used to determine the status of each of the steps during the polishing run.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: A method, system and medium is provided for enabling improved control systems. An error, or deviation from a target result, is observed for example during manufacture of semiconductor chips. The error within standard deviation is caused by two components: a white noise component and a signal component (such as systematic errors). The white noise component is, e.g., random noise and therefore is relatively non-controllable. The systematic error component, in contrast, may be controlled by changing the control parameters. A ratio between the two components is calculated autoregressively. Based on the ratio and using the observed or measured error, the actual value of the error caused by the systematic component is calculated utilizing an autoregressive stochastic sequence. The actual value of the error is then used in determining when and how to change the control parameters.

Abstract: Methods and apparatus are provided for processing a substrate with a bilayer barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a nitrogen containing barrier layer on a substrate surface and then depositing a nitrogen free barrier layer thereon. The barrier layer may be deposited over dielectric materials, conductive materials, or both. The bilayer barrier layer may also be used as an etch stop, an anti-reflective coating, or a passivation layer.

Abstract: A silicon oxide film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A liquid Si—C—O—H precursor is vaporized. A flow of the vaporized liquid Si—C—O—H precursor is provided to the substrate processing chamber. A gaseous oxidizer is also flowed to the substrate processing chamber. A deposition plasma is generated inductively from the precursor and the oxidizer in the substrate processing chamber, and the silicon oxide film is deposited over the substrate and within the gap with the deposition plasma.

Abstract: A chemical mechanical polishing apparatus includes two optical systems which are used serially to determine polishing endpoints. The first optical system includes a first light source to generate a first light beam which impinges on a surface of the substrate, and a first sensor to measure light reflected from the surface of the substrate to generate a measured first interference signal. The second optical system includes a second light source to generate a second light beam which impinges on a surface of the substrate and a second sensor to measure light reflected from the surface of the substrate to generate a measured second interference signal. The second light beam has a wavelength different from the first light beam.

Abstract: A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.

Abstract: Techniques for removing a substrate from a polishing pad are described. A substrate is pulled away from the polishing pad such that the edges of the substrate are pulled away from the polishing pad before the center of the substrate is pulled from the polishing pad.

Abstract: A system, method, and computer program product for chemical mechanical polishing a substrate in which initially a plurality of predetermined pressures are applied to a plurality of regions of the substrate. A plurality of portions of the substrate are monitored during polishing with an in-situ monitoring system. If the difference in thickness between two portions of the substrate exceeds a predetermined threshold, a plurality of adjusted pressures are calculated in a closed-loop control system, and the plurality of adjusted pressures are applied to the plurality of regions of the substrate. The predetermined threshold includes an initial threshold for the start of the polishing process and a second threshold for a period of polishing after the start of the polishing process.

Abstract: The present invention is directed to the design of a plasma CVD chamber which provides more uniform conditions for forming thin CVD films on a substrate. In one embodiment, an apparatus for processing semiconductor substrates comprises a chamber defining a plasma processing region therein. The chamber includes a bottom, a side wall, and a dome disposed on top of the side wall. The dome has a dome top and having a side portion defining a chamber diameter. A top RF coil is disposed above the dome top. A side RF coil is disposed adjacent the side portion of the dome. The side RF coil is spaced from the top RF coil by a coil separation. A ratio of the coil separation to the chamber diameter is at least about 0.15, more desirably about 0.2–0.25.

Abstract: Aspects of the invention generally provide a method for polishing a material layer using electrochemical deposition techniques, electrochemical dissolution techniques, polishing techniques, and/or combinations thereof. In one aspect of the invention, the polishing method comprises applying a separate electrical bias, such as a voltage, to each of a plurality of zones of an electrode. Determining the separate biases comprises determining a time that at least one portion of the material layer is associated with each of the zones of the counter-electrode.