Abstract: Methods and apparatus of controlling a temperature of components in a process chamber that is heated by a plasma or a heater and cooled by a coolant flow through a heat exchanger. An apparatus, for example, can include a chuck assembly and/or a plasma source including a respective cooling plate; a proportional bypass valve connected between the respective cooling plate and a heat exchanger; a temperature sensor configured to measure a temperature of the coolant through the outlet channel of the respective cooling plate; and a controller that receives a measured temperature from the temperature sensor measuring, and in response to receiving the measured temperature controls a rate of flow of the coolant through the first coolant output line and the second coolant output line of the proportional bypass valve.

Abstract: Embodiments of the present disclosure include an apparatus and methods for the plasma processing of a substrate. Some embodiments are directed to a plasma processing chamber. The plasma processing chamber generally includes a planar coil region comprising a plurality of planar coils, a first power supply circuit coupled to at least two of the plurality of planar coils, a concentric coil region at least partially surrounding the planar coil region, and a second power supply circuit coupled to at least two of a plurality of concentric coils. The first power supply circuit may be configured to bias the at least two of the plurality of planar coils to affect a plasma in a center region of the plasma processing chamber, and the second power supply circuit may be configured to bias the at least two of the plurality of concentric coils to affect the plasma in an outer region.

Abstract: There is provided a method and a system configured obtain an image of a semiconductor specimen including one or more arrays, each including repetitive structural elements, and one or more regions, each region at least partially surrounding a corresponding array and including features different from the repetitive structural elements, wherein the PMC is configured to, during run-time scanning of the semiconductor specimen, perform a correlation analysis between pixel intensity of the image and pixel intensity of a reference image informative of at least one of the repetitive structural elements, to obtain a correlation matrix, use the correlation matrix to distinguish between one or more first areas of the image corresponding to the one or more arrays and one or more second areas of the image corresponding the one or more regions, and output data informative of the one or more first areas of the image.

Abstract: Implementations disclosed describe, among other things, a system and a method of scanning a substrate with a beam of light and detecting for each of a set of locations of the substrate, a respective one of a set of intensity values associated with a beam of light reflected from (or transmitted through) the substrate. The detected intensity values are used to determine a profile of a thickness of the substrate.

Abstract: Disclosed herein is a method for non-destructive hybrid acousto-optic and scanning electron microscopy-based metrology. The method includes: (i) obtaining acousto-optic and scanning electron microscopy measurement data of an inspected structure on a sample; (ii) processing the measurement data to extract values of key measurement parameters corresponding to the acousto-optic measurement data and the scanning electron microscopy measurement data, respectively; and (iii) obtaining estimated values of one or more structural parameters of the inspected structure by inputting the extracted values into an algorithm, which is configured to jointly process the extracted values to output estimated values of the one or more structural parameters.

Abstract: A system and method of receiving HDLC communications is disclosed. The system measures the pulse width of the incoming signal and converts each pulse into a series of bits, based on its pulse width. In this way, the reception of the HDLC communication is not dependent on any particular clock rate and is adaptable. The system takes advantages of the fact that the flag is a string of six consecutive bits that are all “1”. Thus, the longest positive pulse width may be used to determine the bit rate. This allows the system to operate over a very broad range of data rates.

Abstract: Methods of semiconductor processing may include forming plasma effluents. The plasma effluents may then contact a carbon-containing hardmask and an oxide cap. The plasma effluents can etch one or more features in the oxide cap through one or more apertures of the carbon-containing hardmask. Etching can create a tapered profile for one or more features in the oxide cap. The one or more features can be characterized by a critical dimension at the bottom of the one or more features. The critical dimension can be less than or about 80% of a width of the one or more apertures.

Abstract: Exemplary semiconductor processing systems may include a chamber body having a bottom plate. The systems may include a substrate support disposed within the chamber body. The substrate support may include a support plate and a shaft. The shaft may include a cooling hub that extends through the bottom plate. The shaft may include a ground shaft that is seated atop the cooling hub. The ground shaft may include a ceramic material. The systems may include an inner isolator coupled with a bottom of the support plate. The inner isolator may define an aperture therethrough that receives the shaft. The systems may include an outer isolator that is seated atop the inner isolator. Each of the inner isolator and the outer isolator may include a ceramic material.

Abstract: Embodiments of the present technology may include semiconductor processing methods and systems. Methods and systems may include providing a substrate to a processing region of a semiconductor processing chamber, where the substrate includes one or more alternating pairs of a semiconductor material layer and a sacrificial material layer. Methods include forming one or more vertically extending features through the one or more alternating pairs of semiconductor material layer and sacrificial material layer, forming one or more sidewalls having alternating exposed lateral ends of the semiconductor material and the sacrificial material. Methods include forming a protective material layer over the exposed lateral ends of the semiconductor material layer. Methods include laterally recessing at least a portion of the sacrificial material layer from the one or more vertically extending features and trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

Abstract: Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a flexible membrane coupled with the carrier body. The flexible membrane may include a substrate-receiving surface that faces away from the carrier body. The substrate-receiving surface may include a plurality of gripping elements that protrude away from the substrate-receiving surface. Each of the plurality of gripping elements may have a maximum lateral dimension that is no greater than 2 mm.

Abstract: Exemplary anneal chambers may include a base that defines a chamber interior. The base may include a cooling plate within the chamber interior. The base and the cooling plate may be integral with one another. The chambers may include a lid that is coupled with the base. The chambers may include a heater plate mounted in the chamber interior alongside the cooling plate. The chambers may include a transfer hoop movably coupled within the chamber interior. The base may define a first transfer hoop recess about at least a portion of the heater plate. The base may define a second transfer hoop recess about at least a portion of the cooling plate.

Abstract: Exemplary substrate processing system faceplates may include a plate that is characterized by a first surface and a second surface opposite the first surface. The second surface may define a plurality of recesses that extend through a portion of a thickness of the plate. The plate may define a plurality of apertures through the thickness of the plate. Each aperture may extend through a bottom surface of one recess of the plurality of recesses. Each recess may have a greater diameter than the aperture extending through the bottom surface of the recess. The faceplate may include a plurality of shape-memory actuators. Each shape-memory actuator may be seated within a respective one of the plurality of recesses. Each shape-memory actuator may define an actuator aperture. A diameter of the actuator aperture each shape memory actuator may be variable.

Abstract: Exemplary semiconductor processing systems may include a chamber body having sidewalls and a base. The semiconductor processing systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate. The substrates support may include a shaft coupled with the support plate. The semiconductor processing systems may include a liner positioned within the chamber body and positioned radially outward of a peripheral edge of the support plate. An inner surface of the liner may include an emissivity texture.

Abstract: Disclosed herein is a method for non-destructive depth-profiling including projecting a pulsed pump beam into a specimen, projecting a pulsed probe beam thereinto, and sensing light returned therefrom to obtain a measured signal. Each probe pulse is configured to undergo Brillouin scattering off a primary acoustic pulse induced by the directly preceding pump pulse, so as to be scattered there off at a respective depth within the specimen. The method further includes executing an optimization algorithm configured to receive as inputs the measured signal, and/or a processed signal obtained therefrom, and output values of structural parameter(s) characterizing the specimen through minimization of a cost function indicative of a difference between the measured signal and a simulated signal obtained using a forward model simulating the scattering of a pulsed probe beam off at least the primary acoustic pulses.

Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing a gapfill material, such as titanium nitride (TiN), in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as FinFETs, GAAs, and the like, with a gapfill material without creating a seam. One or more embodiments include selective deposition processes using a carbon (C) layer in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion energy of less than or about 50 eV, or a combination thereof. Flowing the plasma effluents into a processing region of the semiconductor processing chamber. The microwave applicator includes a resonator body and a plate, where the resonator body is formed from or coated with a first dielectric material and the plate is formed from or coated with a second dielectric material.

Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.

Abstract: Exemplary substrate support assemblies may include a support plate that comprises a substrate support surface. The assemblies may include a support stem coupled with the support plate. A channel may be defined through at least a portion of a length of the support stem and extends through the substrate support surface. A temperature sensor assembly may be disposed within the channel. The temperature sensor assembly may include a light pipe disposed within the channel such that a top end of the light pipe extending through at least a portion of the support plate. The temperature sensor assembly may include a sensor that is coupled with a bottom end of the light pipe.

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the ultimate tensile strength and the elongation at break is greater than or about 2,000.