Abstract: A method of etching a silicon-containing layer 170 on a substrate 45 comprises the steps of placing the substrate 45 on a support 75 in a process chamber 50. The substrate 45 is exposed to an energized process gas comprising a bromine-containing gas, a chlorine-containing gas, an inorganic fluorinated gas, and an oxygen gas. The volumetric flow ratio of the gas constituents is selected so that the energized process gas etches regions 180a,b having different concentrations of dopant in the polysilicon layer 170 at substantially the same etching rate. Optionally, the gas composition is also tailored to simultaneously clean off etch residue from the internal surfaces of a process chamber 50 during etching of the substrate 45.

Abstract: A vacuum seal and fluid bearing apparatus for reducing the distortion of the bearing surfaces of a gas bearing is described. The apparatus includes a stator attached around an aperture in a vacuum housing and having a first planar fluid bearing surface. A movable member for closing the vacuum housing aperture having a second fluid bearing surface extending parallel to the first bearing surface is adapted to be supported spaced from the first bearing surface by a bearing fluid. A vacuum seal is provided between the movable member and the stator. In use, a force due to atmospheric pressure acts on the movable member in a direction normal to the bearing surfaces and a movable member includes a pressure relief structure to reduce any bending moment produced in the movable member by the force.

Abstract: The useful lifetime of a fixed abrasive article is extended and wafer-to-wafer uniformity enhanced by preconditioning a fixed abrasive element and/or periodic conditioning after initial wafer polishing. Embodiments include preconditioning by forced removal of an upper binder-rich portion of the fixed abrasive elements to expose abrasive particles having a similar concentration as the bulk concentration at about one half the height of the elements. Embodiments further include periodic conditioning after initial wafer polishing by forced removal of an upper portion of the fixed abrasive elements.

Abstract: A method and apparatus for heating a loadlock to inhibit the formation of contaminants within the loadlock. At least one heater is attached to the walls of the loadlock to boil contaminants from the surfaces within the loadlock. These desorbed contaminants are exhausted from the loadlock by a vacuum pump. Alternatively, a purge gas can be supplied to the loadlock while the loadlock is being heated. The flow of purge gas flushes the desorbed contaminants from the loadlock.

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of platinum electrodes. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the platinum electrode layer by employing a plasma of an etchant gas comprising nitrogen and a halogen (e.g. chlorine), and a gas selected from the group consisting of a noble gas (e.g. argon), BCl3, HBr, SiCl4 and mixtures thereof. The substrate may be heated in a reactor chamber having a dielectric window including a deposit-receiving surface having a surface finish comprising a peak-to-valley roughness height with an average height value of greater than about 1000 Å.

Abstract: The present invention generally provides a robot that can transfer workpieces, such as silicon wafers, at increased speeds and accelerations and decelerations. More particularly, the present invention provides a robot wrist associated with the robot arm for mechanically clamping a workpiece to a workpiece handling member attached to the arm. The workpiece clamp selectively applies sufficient force to hold the workpiece and prevent slippage and damage to the workpiece during rapid rotation and linear movement of the handling member. In one embodiment, a clamp for securing silicon wafers uses two clamp fingers connected to a single flexure member to position and hold the wafer with minimal particle generation and wafer damage. The clamp is designed so that wafers are normally clamped except near full extension of the workpiece handling member to deliver or pick up a wafer.

Abstract: A sensor device, for diagnosing a processing system, generally includes a support platform and one or more sensors mounted on the support platform. The sensor senses a condition, such as direction or inclination or acceleration in one or two axes, of the sensor device and outputs a signal indicative thereof, which is then sent to a transmitter, also mounted to the support platform, for wireless transmission of the signal to a receiver mounted on or near the processing system. The support platform generally has physical characteristics, such as size, profile height, mass, flexibility and/or strength, substantially similar to those of the substrates that are to be processed in the processing system, so the sensor device can be transferred through the processing system in a manner similar to the manner in which production substrates are transferred through the processing system.

Abstract: An apparatus for confining plasma within a process zone of a substrate processing chamber. In one aspect, an apparatus comprises an annular member having an upper mounting surface, an inner confinement wall, and an outer confinement wall. The apparatus is disposed on or otherwise connected to a gas distribution assembly of the processing chamber to prevent plasma edge effects on the surface of a substrate. The apparatus provides a plasma choke aperture that reduces the volume of the process zone around the periphery of the substrate thereby eliminating uneven deposition of material around the edge of the substrate.

Abstract: A method and apparatus for reducing surface sensitivity of a TEOS/O3 SACVD silicon oxide layer, formed over a substrate, that deposits a ramp layer while ramping pressure to a target deposition pressure and deposits an SACVD layer over the ramp layer. In one embodiment, the flow of ozone is stopped during the pressure ramp-up to control the thickness of the ramp layer.

Abstract: A method for reducing the resistivity of a copper layer on a wafer. A moisture containing seed layer of copper is formed over a layer of material on a wafer. The copper seed layer is treated by either heat or ions from a plasma to anneal out moisture thereby reducing its resistivity and improving its adhesion to the underlying layer. A moisture free copper layer is then deposited on top of the “clean” or treated copper seed layer.

Abstract: A method and apparatus for generating an accurate, table phase shift (b) in a sinusoidal signal employs fast analog multiplication to implement the trigonometric relationship sin(&ohgr;t+b)=sin(&ohgr;t)cos(b)+cos(&ohgr;t)sin(b). Cos (&ohgr;t) is generated by accurately shifting a signal sin(&ohgr;t) through 90° using a delay line, for example. Sin(b) and cos(b) are dc signals generated by digital to analogue conversion, using a demanded phase shift (b) whose sine and cosine are obtained from look-up tables. A controller for controlling a phase shift in an rf cavity is also disclosed and operates on the basis of the same trigonometrical principle. The amplitude of the signals in the rf cavity is also controllable; fast analogue multipliers are again employed to scale the signal amplitude to a nominal fixed value such as 1 volt.

Abstract: A chuck 28 for holding a substrate 4 comprises a surface 27 capable of receiving the substrate 4, the surface 27 having a gas inlet port 40 and a gas exhaust port 42. A non-sealing protrusion is between the gas inlet port 40 and the gas exhaust port 42. The non-sealing protrusion 44 impedes the flow of heat transfer gas between the gas inlet port 40 and the gas exhaust port 42 without blocking the flow of heat transfer gas. Preferably, a sealing protrusion 46 is provided around the periphery of the chuck 28 to form a substantially gas-tight seal with the substrate 4 to enclose and prevent leakage of heat transfer gas into a surrounding chamber 6.

Abstract: The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and anunonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to form a metal/metal nitride liner/barrier scheme.

Abstract: The present invention provides a method and apparatus for delivering one or more rinse agents to a surface, such as a polishing pad surface and preferably one or more polishing fluids. The invention also provides a method of cleaning one or more surfaces, such as a polishing pad surface and a substrate surface, by delivering a spray of one or more rinse agents to the surface and, preferably, causing the rinse agent to flow across the surface from a central region to an outer region where unwanted debris and material is collected.

Abstract: This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

Abstract: A carrier head with a flexible member connected to a base to define a first chamber, a second chamber and a third chamber. A lower surface of the flexible member provides a substrate receiving surface with an inner portion associated with the first chamber, a substantially annular middle portion surrounding the inner portion and associated with the second chamber, and a substantially annular outer portion surrounding the middle portion and associated with the third chamber. The width of the cuter portion may be significantly less than the width of the middle portion. The carrier head may also includea flange connected to a drive shaft and a gimbal pivotally connecting the flange to the base.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: A wafer polishing head utilizes a wafer backing member having a wafer facing pocket which is sealed against the wafer and is pressurized with air or other fluid to provide a uniform force distribution pattern across the width of the wafer inside an edge seal feature at the perimeter of the wafer to urge (or press) the wafer uniformly toward a polishing pad. Wafer polishing is carried out uniformly without variations in the amount of wafer material across the usable area of the wafer. A frictional force between the seal feature of the backing member and the surface of the wafer transfers rotational movement of the head to the wafer during polishing. A pressure controlled bellows supports and presses the wafer backing member toward the polishing pad and accommodates any dimensional variation between the polishing head and the polishing pad as the polishing head is moved relative to the polishing pad.

Abstract: The present invention pertains to a method for depositing built-up structures on the surface of patterned masking material used for semiconductor device fabrication. Such built-up structures are useful in achieving critical dimensions in the fabricated device. The composition of the built-up structure to be fabricated is dependant upon the plasma etchants used during etching of underlying substrates and on the composition of the substrate material directly underlying the masking material. When the patterned mask is to be used to transfer a pattern to an underlying polysilicon layer, the polysilicon may be etched using a plasma source gas which is a combination of Cl2, HBr, and optionally O2. An alternative etchant plasma utilizes a plasma source gas which is a combination of SF6, Cl2 and N2. We have developed an alternative method for depositing built-up structures depending on whether the polysilicon plasma etchant includes an HBr component.

Abstract: The present invention provides a load lock having a vertically movable lid, an internal robot, and a wafer lifting mechanism and further provides a method of transferring wafers through a load lock directly to a process chamber. An atmospheric transfer robot shuttles wafers to and from the lifting mechanism while the lid is raised and the lifting mechanism then transfers wafers to and from the internal robot. The load lock is directly attached to a process chamber and communicates therewith via a slit valve which is selectively opened and closed. The internal robot is extended and retracted through the slit valve aperture in order to transfer a wafer to and from the process chamber. In one embodiment the lifting mechanism is comprised of vertically movable lift pins disposed through the bottom of the load lock. In another embodiment the lifting mechanism includes two pairs of lift forks disposed through the cover of the load lock.