Patents Assigned to Applied Materials
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Patent number: 11410873Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.Type: GrantFiled: November 20, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
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Patent number: 11408075Abstract: Embodiments of the present disclosure generally relate to a batch processing chamber that is adapted to simultaneously cure multiple substrates at one time. The batch processing chamber includes multiple processing sub-regions that are each independently temperature controlled. The batch processing chamber may include a first and a second sub-processing region that are each serviced by a substrate transport device external to the batch processing chamber. In addition, a slotted cover mounted on the loading opening of the batch curing chamber reduces the effect of ambient air entering the chamber during loading and unloading.Type: GrantFiled: October 18, 2018Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Adib Khan, Shankar Venkataraman, Jay D. Pinson, II, Jang-Gyoo Yang, Nitin Krishnarao Ingle, Qiwei Liang
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Patent number: 11408068Abstract: Methods for depositing tellurium-containing films on a substrate are described. The substrate is exposed to a tellurium precursor and a reactant to form the tellurium-containing film (e.g., elemental tellurium, tellurium oxide, tellurium carbide, tellurium silicide, germanium telluride, antimony telluride, germanium antimony telluride). The exposures can be sequential or simultaneous.Type: GrantFiled: February 1, 2021Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Thomas Knisley, Keenan N. Woods, Mark Saly, Charles H. Winter, Apoorva Upadhyay
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Patent number: 11410881Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.Type: GrantFiled: June 28, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang, Lu Chen
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Patent number: 11410860Abstract: Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.Type: GrantFiled: January 8, 2021Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Dmitry Lubomirsky, Srinivas Nemani, Ellie Yieh, Sergey G. Belostotskiy
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Patent number: 11411125Abstract: A selector device may include a first electrode, a tunneling layer, and a ferroelectric layer. The tunneling layer may be between the first electrode and the ferroelectric layer, and a thickness and dielectric constant of the tunneling layer relative to a thickness and dielectric constant of the ferroelectric layer may cause a depolarizing electric field induced in the first tunneling layer to be greater than or approximately equal to an electric field induced in an opposite direction by ferroelectric dipoles in the ferroelectric layer when a voltage is applied across the selector device. The device may also include a second electrode, and the ferroelectric layer may be between the tunneling layer and the second electrode. A second ing layer may also be added between the ferroelectric layer and the second electrode for bipolar selectors.Type: GrantFiled: October 6, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventor: Milan Pe{hacek over (s)}ić
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Patent number: 11410869Abstract: Electrostatic chucks (ESCs) for reactor or plasma processing chambers, and methods of fabricating ESCs, are described. In an example, a substrate support assembly includes a ceramic bottom plate having heater elements therein, the ceramic bottom plate composed of alumina having a first purity. The substrate support assembly also includes a ceramic top plate having an electrode therein, the ceramic top plate composed of alumina having a second purity higher than the first purity. A bond layer is between the ceramic top plate and the ceramic bottom plate. The ceramic top plate is in direct contact with the bond layer, and the bond layer is in direct contact with the ceramic bottom plate.Type: GrantFiled: February 22, 2021Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventor: Vijay D. Parkhe
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Patent number: 11411039Abstract: Generally, examples described herein relate to methods and processing chambers and systems for forming a stacked pixel structure using epitaxial growth processes and device structures formed thereby. In an example, a first sensor layer is epitaxially grown on a crystalline surface on a substrate. A first isolation structure is epitaxially grown on the first sensor layer. A second sensor layer is epitaxially grown on the first isolation structure. A second isolation structure is epitaxially grown on the second sensor layer. A third sensor layer is epitaxially grown on the second isolation structure.Type: GrantFiled: May 19, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Papo Chen, John Boland, Schubert S. Chu, Errol Antonio C. Sanchez, Stephen Moffatt
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Publication number: 20220248500Abstract: A method of providing power to a plurality of heaters in multiple zones for wafer-processing equipment may include causing a voltage to be supplied to a plurality of power leads configured to supply the voltage to a plurality of different heating zones in a pedestal, causing current to be received from the plurality of different heating zones through a return lead that is shared by the plurality of power leads, and causing a polarity of the voltage provided to the plurality of power leads to switch. The switching frequency may be configured such that a DC chucking operation can be active at the same time to hold a substrate to the pedestal. Duty cycling the heating zones that share the return lead may minimize the current through the shared return lead.Type: ApplicationFiled: February 4, 2021Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Uwe P. Haller, Kiyki-Shiy N. Shang, Dmitry A. Dzilno
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Publication number: 20220246558Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Chintan Buch, Roman Gouk, Steven Verhaverbeke
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Publication number: 20220248523Abstract: An apparatus may include a drift tube assembly, the drift tube assembly defining a triple gap configuration, and arranged to accelerate and transmit an ion beam along abeam path. The apparatus may include a resonator, to output an RF signal to the drift tube assembly, and an RF quadrupole triplet, connected to the drift tube assembly, and arranged circumferentially around the beam path.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Frank Sinclair, Wai-Ming Tam, Costel Biloiu, William Davis Lee
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Publication number: 20220246471Abstract: Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.Type: ApplicationFiled: April 14, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Anqing Cui, Dien-Yeh Wu, Wei V. Tang, Yixiong Yang, Bo Wang
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Publication number: 20220246742Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.Type: ApplicationFiled: January 25, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Myungsun Kim
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Publication number: 20220246746Abstract: Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.Type: ApplicationFiled: February 4, 2021Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventor: Andrew Michael Waite
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Publication number: 20220243331Abstract: Aspects of the present disclosure provide systems and apparatuses for a substrate processing assembly with a laminar flow cavity gas injection for high and low pressure. A dual gas reservoir assembly is provided in a substrate processing chamber, positioned within a lower shield assembly. A first gas reservoir is in fluid communication with a processing volume of the substrate processing assembly via a plurality of gas inlet, positioned circumferentially about the processing volume. A second gas reservoir is positioned circumferentially about the first gas reservoir, coupled therewith via one or more reservoir ports. The second gas reservoir is in fluid communication with a first gas source. A recursive path gas assembly is positioned in an upper shield body adjacent to an electrode to provide one or more gases to a dark space gap.Type: ApplicationFiled: February 3, 2021Publication date: August 4, 2022Applicants: Applied Materials, Inc., Applied Materials, Inc.Inventors: Kirankumar Neelasandra SAVANDAIAH, Srinivasa Rao YEDLA, Nitin Bharadwaj SATYAVOLU, Ganesh SUBBUSWAMY, Devi Raghavee VEERAPPAN, Thomas BREZOCZKY
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Publication number: 20220246432Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: Applied Materials, Inc.Inventors: Srinivas Gandikota, Abhijit Basu Mallick, Swaminathan Srinivasan, Rui Cheng, Susmit Singha Roy, Gaurav Thareja, Mukund Srinivasan, Sanjay Natarajan
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Patent number: 11404248Abstract: Embodiments include a modular microwave source. In an embodiment, the modular microwave source comprises a voltage control circuit, a voltage controlled oscillator, where an output voltage from the voltage control circuit drives oscillation in the voltage controlled oscillator. The modular microwave source may also include a solid state microwave amplification module coupled to the voltage controlled oscillator. In an embodiment, the solid state microwave amplification module amplifies an output from the voltage controlled oscillator. The modular microwave source may also include an applicator coupled to the solid state microwave amplification module, where the applicator is a dielectric resonator.Type: GrantFiled: August 14, 2020Date of Patent: August 2, 2022Assignee: Applied Materials, Inc.Inventors: Philip Allan Kraus, Thai Cheng Chua
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Patent number: 11401602Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.Type: GrantFiled: January 4, 2021Date of Patent: August 2, 2022Assignee: Applied Materials, Inc.Inventors: Byunghoon Yoon, Seshadri Ganguli, Xi Cen
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Patent number: 11404296Abstract: Embodiments disclosed herein include a method of determining the position of a sensor wafer relative to a pedestal. In an embodiment, the method comprises placing a sensor wafer onto the pedestal, wherein the sensor wafer comprises a first surface that is supported by the pedestal, a second surface opposite the first surface, and an edge surface connecting the first surface to the second surface, wherein a plurality of sensor regions are formed on the edge surface, and wherein the pedestal comprises a major surface and an annular wall surrounding the sensor wafer. In an embodiment, the method further comprises determining a gap distance between each of the plurality of sensor regions and the annular wall. In an embodiment, the method may further comprise determining a center-point offset of a center-point of the sensor wafer relative to a center point of the annular wall from the gap distances.Type: GrantFiled: August 20, 2019Date of Patent: August 2, 2022Assignee: Applied Materials, Inc.Inventors: Charles G. Potter, Anthony D. Vaughan
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Patent number: 11404314Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.Type: GrantFiled: October 16, 2020Date of Patent: August 2, 2022Assignee: Applied Materials, Inc.Inventors: Sony Varghese, M. Arif Zeeshan, Shantanu Kallakuri, Kelvin Chan
