Abstract: Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Abstract: An ion source chamber with an embedded heater is disclosed. The heater comprises a radiant heater, such as a heat lamp or light emitting diodes, and is disposed within the ion source chamber. The radiant heat from the heater warms the interior surfaces of the ion source chamber. Further, the ion source chamber is designed such that the plasma is generated in a portion of the ion source chamber that does not contain the heater. Additionally, a controller may be in communication with the heater so as to maintain the ion source chamber at a desired temperature when a plasma is not being generated in the ion source chamber.

Abstract: Methods of monitoring a plasma while processing a semiconductor substrate are described. In embodiments, the methods include determining the difference in power between the power delivered from the plasma power supply and the power received by the plasma in a substrate processing chamber. The power received may be determined using a V/I sensor positioned after the matching circuit. The power reflected or the power lost is the difference between the delivered power and the received power. The process may be terminated by removing the delivered power if the reflected power is above a setpoint. The VRF may further be fourier transformed into frequency space and compared to the stored fourier transform of a healthy plasma process. Missing frequencies from the VRF fourier transform may independently or further indicate an out-of-tune plasma process and the process may be terminated.

Abstract: One or more embodiments described herein generally relate to selective deposition of substrates in semiconductor processes. In these embodiments, a precursor is delivered to a process region of a process chamber. A plasma is generated by delivering RF power to an electrode within a substrate support surface of a substrate support disposed in the process region of the process chamber. In embodiments described herein, delivering the RF power at a high power range, such as greater than 4.5 kW, advantageously leads to greater plasma coupling to the electrode, resulting in selective deposition to the substrate, eliminating deposition on other process chamber areas such as the process chamber side walls. As such, less process chamber cleans are necessary, leading to less time between depositions, increasing throughput and making the process more cost-effective.

Abstract: The present disclosure relates to methods and apparatus for treating vacuum processing system exhaust gases. In addition, methods and apparatus for maintenance of foreline plasma reactor subsystems are disclosed. In some embodiments, an apparatus for treating an exhaust gas in a foreline of a vacuum processing system includes a plasma source coupled with a foreline of a process chamber, a treatment agent source coupled with the plasma source, and a downstream trap to cool an exhaust stream and trap particles in the exhaust stream. In some embodiments, multiple foreline plasma reactor subsystems are used with a vacuum processing system, and one foreline plasma reactor subsystem can be isolated and maintained (e.g., cleaned) while exhaust gas treatment continues in another foreline plasma reactor subsystem and processing continues in the vacuum processing system.

Abstract: A method for improving the beam current for certain ion beams, and particularly germanium and argon, is disclosed. The use of argon as a second gas has been shown to improve the ionization of germane, allowing the formation of a germanium ion beam of sufficient beam current without the use of a halogen. Additionally, the use of germane as a second gas has been shown to improve the beam current of an argon ion beam.

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.

Abstract: Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.

Abstract: Embodiments of the present disclosure relate to forming a two-dimensional crystalline dichalcogenide by positioning a substrate in an annealing apparatus. The substrate includes an amorphous film of a transition metal and a chalcogenide. The film is annealed at a temperature from 500° C. to 1200° C. In response to the annealing, a two-dimensional crystalline structure is formed from the film. The two-dimensional crystalline structure is according to a formula MX2, M includes one or more of molybdenum (Mo) or tungsten (W) and X includes one or more of sulfur (S), selenium (Se), or tellurium (Te).

Abstract: Implementations described herein generally relate to low melting temperature metal or alloy metal deposition and processing. More particularly, the implementations described herein relate to methods and systems for low melting temperature metal or alloy metal deposition and processing for printed electronics and electrochemical devices. In yet another implementation, a method is provided. The method comprises exposing a molten metal source to a purification process to remove unwanted quantities of contaminants, delivering the filtered molten metal to a three dimensional printing device, and forming a metal film on a substrate by printing the filtered molten metal on the substrate. The purification process comprises delivering the molten metal to a filter assembly, wherein the filter assembly includes at least one of: a skimmer device, a metal mesh filter, and a foam filter, and filtering the molten metal through the filter assembly.

Abstract: An electronic device manufacturing system includes a motion control system for calibrating a gap between surfaces of process chamber or loadlock components by moving those component surfaces into direct contact with each other. The component surfaces may include a surface of a substrate and/or a substrate support and a surface of process delivery apparatus, which may be, e.g., a pattern mask and/or a plasma or gas distribution assembly. The motion control system may include a motion controller, a software program executable by the motion controller, a network, one or more actuator drivers, a software program executable by the one or more actuator drivers, one or more actuators, and one or more feedback devices. Methods of calibrating a gap via direct contact of process chamber or loadlock component surfaces are also provided, as are other aspects.

Abstract: Embodiments of this disclosure describe a feedback loop that can be used to maintain a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate. The system described herein consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

Abstract: Embodiments of the present disclosure generally relate to methods for conditioning an interior wall surface of a remote plasma generator. In one embodiment, a method for processing a substrate is provided. The method includes exposing an interior wall surface of a remote plasma source to a conditioning gas that is in excited state to passivate the interior wall surface of the remote plasma source, wherein the remote plasma source is coupled through a conduit to a processing chamber in which a substrate is disposed, and the conditioning gas comprises an oxygen-containing gas, a nitrogen-containing gas, or a combination thereof. The method has been observed to be able to improve dissociation/recombination rate and plasma coupling efficiency in the processing chamber, and therefore provides repeatable and stable plasma source performance from wafer to wafer.

Abstract: A processing chamber may include a gas distribution member, a metal ring member below the gas distribution member, and an isolating assembly coupled with the metal ring member and isolating the metal ring member from the gas distribution member. The isolating assembly may include an outer isolating member coupled with the metal ring member. The outer isolating member may at least in part define a chamber wall. The isolating assembly may further include an inner isolating member coupled with the outer isolating member. The inner isolating member may be disposed radially inward from the metal ring member about an central axis of the processing chamber. The inner isolating member may define a plurality of openings configured to provide fluid access into a radial gap between the metal ring member and the inner isolating member.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

Abstract: A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device, and a plurality of gates formed around the plurality of fins to form a plurality of fin field-effect transistors (FinFETs). The plurality of FinFETs may form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses may include two or more of the plurality of gates. Each of the one or more artificial neurons comprises one of the plurality of gates.

Abstract: Described are isolation valves, and chamber systems incorporating and methods of using the isolation valves. In some embodiments, an isolation valve may include a valve body and a flapper assembly. The valve body may define a first fluid volume, a second fluid volume, and a seating surface. The flapper assembly may include a flapper disposed inside the valve body having a flapper surface complimentary to the seating surface. The flapper may be pivotable within the valve body to a first position such that the flapper surface may be away from the seating surface to allow fluid flow between the first fluid volume and the second fluid volume. The flapper may be pivotable within the valve body to a second position such that the flapper surface may be proximate the seating surface to form a non-contact seal to restrict fluid flow between the first fluid volume and the second fluid volume.

Abstract: Described are semiconductor devices, methods of manufacturing, and methods for device patterning. More particularly, a subtractive interconnect patterning method is described. A subtractive interconnect patterning is used in place of damascene interconnect patterning.

Abstract: Methods of depositing an encapsulation stack without damaging underlying layers are discussed. The encapsulation stacks are highly conformal, have low etch rates, low atomic oxygen concentrations, good hermeticity and good adhesion. These films may be used to protect chalcogen materials in PCRAM devices. Some embodiments utilize a two-step process comprising a first ALD process to form a protective layer and a second plasma ALD process to form an encapsulation layer.