Abstract: In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.

Abstract: The present invention pertains to methods of depositing low stress/high index multi-layer films on a substrate using an HDP-CVD process. The multi-layer films include two lining layers and a bulk gap-fill layer and the HDP-CVD process employs a reduced substrate bias power during deposition of at least the second lining layer. Deposition of the three layers occurs at reduced deposition temperatures which further reduces the stress of the multi-layer film. The lower stress results in less defectivity which improves the films ability to maintain optical confinement of radiation.

Abstract: In a first aspect, an apparatus is provided for opening a substrate carrier door of a substrate carrier. The apparatus includes a supporting member adapted to (1) support the substrate carrier door at a load port; (2) allow removal of the door from the substrate carrier; and (3) pivot the removed door below a bottom surface of the substrate carrier. Numerous other aspects are provided.

Abstract: A substrate processing chamber component is capable of being exposed to an energized gas in a process chamber. The component has an underlying structure and first and second coating layers. The first coating layer is formed over the underlying structure, and has a first surface with an average surface roughness of less than about 25 micrometers. The second coating layer is formed over the first coating layer, and has a second surface with an average surface roughness of at least about 50 micrometers. Process residues can adhere to the surface of the second coating layer to reduce the contamination of processed substrates.

Abstract: The invention includes the structure of a multilayer protective coating, which may have, among other properties, scratch resistance, UV absorption, and an effective refractive index matched to a polymer substrate such as polycarbonate. Each layer may contain multiple components consisting of organic and inorganic materials. The multilayer protective coating includes interleaved organic layers and inorganic layers. The organic layers may have 20% or more organic compounds such as SiOxCyHz. The inorganic layers may have 80% or more inorganic materials, such as SiO2, SiOxNy, and ZnO, or mixtures thereof. Each layer of the multilayer protective coating is a micro layer and may have a thickness of 5 angstroms or less in various embodiments. The multilayer protective coating may contain in the order of hundreds or thousands of micro layers, depending upon the design requirement of applications. In each micro layer, the components may have substantially continuous variations in concentration.

Abstract: Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

Abstract: The invention relates to a method for operating a magnetron sputter cathode, in particular a tube cathode or several tube cathodes forming an array. In such cathodes a target passes through a magnetic field, whereby induction currents flow in the target which distort the magnetic field. This results in the nonuniform coating of a substrate. By having the relative movement between magnetic field and target alternately reverse its direction, the effect of the magnetic field distortion can be compensated. This yields greater uniformity of the coating on a substrate to be coated.

Abstract: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.

Abstract: A carrier head that has a base assembly, a retaining ring assembly, a carrier ring, and a flexible membrane is described. A retaining ring assembly has a flexible membrane shaped to provide an annular chamber and an annular retaining ring, wherein annular concentric projections of the flexible membrane are sized to fit into annular concentric recesses of the annular retaining ring.

Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

Abstract: Embodiments of an apparatus for sealing a substrate transfer passage in a chamber are provided. In one embodiment, an apparatus for sealing a substrate transfer passage in a chamber includes an elongated door member having a convex sealing face and a backside. In another embodiment, a chamber having an apparatus for sealing a substrate transfer passage is provided that includes a chamber body having an interior volume, at least one substrate access defined through the chamber body configured to allow passage of a large area substrate therethrough, and a door member having a convex sealing face moveable between a first position that covers the substrate transfer port and a second position clear of the substrate transfer port. In yet another embodiment, the chamber body may be a load lock chamber.

Abstract: A method for imaging a surface includes generating a traveling lens in an acousto-optic material and incorporating a traveling mask into a portion of the traveling lens so as to produce a composite traveling lens. The method further includes irradiating the composite traveling lens so as to produce a composite focused beam having a spatial variation across the composite focused beam. The composite focused beam is directed onto a region of the surface so as to generate radiation characteristic of the region from the region. The radiation is imaged onto a detector so as to generate a signal characteristic of the region, responsively to the spatial variation.

Abstract: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second substrate with the thermal chemical-vapor-deposition process using the first group-III precursor and the first nitrogen precursor. The first and second substrates are different outer substrates of a plurality of stacked substrates disposed within the processing chamber as a stack so that the first and second layers are deposited on opposite sides of the stack. Deposition of the first layer and deposition of the second layer are performed simultaneously.

Abstract: Aspects of the present invention include a method and an apparatus that may be utilized to reduce dishing and improve cleaning efficiency of a material layer residue (e.g., copper residual) by varying a substrate potential in a substrate processing system. For example, by utilizing multiple polishing steps and applying different voltages (e.g., while a substrate is being in a polishing station), ECMP can be used to effectively reduce dishing and it can be used to enhance copper residual cleaning as well as minimizing a possibility of arcing, which can occur at the end of the polishing process, when a substrate is moved from a polishing station.

Abstract: A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.

Abstract: A band to band transfer module according to the present invention may be used with a substrate carrier transport system, or other systems, to transfer substrate carriers (e.g., small lot substrate carriers) from one conveyor to another conveyor or between two points on the same conveyor. The transfers (e.g., pick and place) of the substrate carriers may be made between conveyors traveling at different speeds. Numerous other aspects and features are disclosed.

Abstract: The invention relates to a vacuum treatment plant comprising an evaporator (1) for vacuum coating facilities. The evaporator (1) according to the invention comprises a device for guiding a supply line (4) movable in a gripping direction (A) and intended for gripping and positioning an evaporation boat (3) having a base (22) and further comprises two spacers (18, 19) which the movable supply line (4) flexibly connects to the base (22), with the spacers (18, 19) being disposed on one side each with the movable supply line (4) and with the other side on the base (22), thus enabling the first supply line (4) to be forcibly guided, and with the spacers (18, 19) having such a length and configuration between the first supply line (4) and the base (22) that the guidance direction (B) is essentially parallel to the gripping direction (A) at least across a small deflection range of the spacers (18, 19).

Abstract: The present invention refers to a method of producing a photovoltaic device having at least one semiconductor unit comprising the following steps: a cleaning of at least one surface of the semiconductor unit by etching; drying of the at least one surface of the semiconductor unit in a substantially oxygen-free or oxygen-depleted environment; and depositing of a passivation layer on the at least one surface as well as to a device for carrying out such a method and to photovoltaic devices produced by this method.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.

Abstract: The present invention provides a non-destructive method for monitoring and calibrating chamber temperature. One embodiment of the present invention provides a method for measuring temperature comprising forming a target film on a test substrate at a first temperature, wherein the target film has one or more properties responsive to thermal exposure, exposing the target film to an environment at a second temperature in a range higher than the first temperature, measuring the one or more properties of the target film after exposing the target film to the environment at the second temperature, and determining the second temperature according to the measured one or more properties.