Abstract: Generating a still image from a sequence of video frames comprises the steps of receiving a sequence of video frames and storing a predetermined number of the sequence of video frames temporally adjacent to an user initiated capture event, the predetermined number of frames being defined as a cliplet. Video capture is performed using cliplets, which are short video segments, preferably in compressed data format. A crop-and-process instruction is added to the cliplet. All processing, handling or storage of the data is cliplet based. Editing instructions are stored with the cliplet allowing editing to be performed by a user at one resolution and then re-performed at a higher resolution at a server where it is printed. Modified reprints of an image can be obtained without resending the images and adequate storage for the cliplets can be assured. Encryption of the cliplets during transmission and storage is facilitated by cliplet-based processing.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A chip scale structure fabricated from known MEMS processes is provided including a pump actuator, a pump volume, pump membrane, a valve membrane, a valve aperture, and a valve actuator. The pump actuator may include a piezoelectric or piezoceramic disk. The valve actuator may be a piezoelectric or piezoceramic disk. A manifold plate with a valve aperture is disposed between the pump membrane and the valve membrane. One or more vacuum chambers are provided along a vacuum flow path or conduit in communication with the one or more vacuum chambers. The flow path comprises an inlet port and an outlet port where the inlet port is in communication with the separately provided vacuum environment. The outlet port is in commemoration with an external environment (e.g. non or lower-vacuum environment) for exhausting gases that are pulled from the separately provided vacuum environment to a separate location.

Abstract: A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

Abstract: An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

Abstract: Piezoelectric elements for power generation and/or actuation are described. An aspect is directed to generators utilizing piezoelectric elements for electrical power generation. Such a generator can use one or more arrays of piezoelectric cantilevers for electrical power generation in conjunction with modulated air pressure used for exciting the cantilevers. The pressure level/modulation and cantilever area can be controlled variables for maximizing the bending, and hence energy generation, of the cantilevers. A further aspect is directed to hydraulic fluid actuators utilizing a pumping mechanism that includes a piezoelectric element. The linear actuators can advantageously utilize the high force and high frequency characteristics of a piezoelectric membrane in conjunction with a large stroke and actuation direction conversion afforded by hydraulic transmission.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract: The invention discloses a device comprising a stack of at least two layers, which may comprise active or passive discrete components, TSOP and/or ball grid array packages, flip chip or wire bonded bare die or the like, which layers are stacked and interconnected to define an integral module. A first and second layer comprise an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive traces terminate at a lateral surface of each of the layers to define an access lead. An interposer structure is disposed between the layers and provides an interposer lateral surface upon which a conductive layer interconnect trace is defined to create an electrical connection between predetermined access leads on each of the layers.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The I/O pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.

Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.

Abstract: Layers suitable for stacking in three dimensional, multilayer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are underfilled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

Abstract: A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.