Stackable layer containing ball grid array package

Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

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Description
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No. 11/825,643, filed Jul. 7, 2007, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

The present invention relates to the dense packaging of electronic circuitry and specifically to the stacking of ball grid array (BGA) format integrated circuit packages. The invention is also suitable for the stacking of fine ball grid array (FBGA) integrated circuit packages, micro-ball grid array packages and for bump-bonded bare die to form stackable layers which can be combined to form multi-layer electronic modules.

The electronics industry continues to seek smaller, denser electronic packaging. An important advance in this regard has been the use of three-dimensional packaging techniques using stacked bare or packaged integrated circuit die.

Most of the background art disclosures describe methods of stacking multiple unpackaged IC chips. Oguchi et al., U.S. Pat. No. 5,332,922, Miyano et al., U.S. Pat. No. 5,440,171, and Choi et al., U.S. Pat. No. 5,677,569, disclose methods of stacking IC chips within a single package. Jeong et al., U.S. Pat. No. 5,744,827 discloses a new type of custom chip packaging which permits stacking, but which does not allow the use of off-the-shelf packaged IC's. Burns, U.S. Pat. No. 5,484,959 shows a method of stacking TSOP packages which requires multiple leadframes attached above and below each TSOP and a system of vertical bus-bar interconnections, but which does not conveniently allow an expansion of the number of vertically interconnecting leads.

The assignee of this application, Irvine Sensors Corporation, has been a leader in developing high-density packaging of IC chips, for use in focal plane modules and for use in a variety of computer functions such as electronic memory. Examples of Irvine Sensors Corp.'s high-density electronic packaging are disclosed in U.S. Pat. No. 4,672,737, to Carson, et al.; U.S. Pat. No. 5,551,629, to Carson et al.; U.S. Pat. No. 5,688,721, to Johnson; U.S. Pat. No. 5,347,428 to Carson, et al.; and U.S. Pat. No. 6,028,352 to Eide, all of which are fully incorporated herein.

The present invention relates to the stacking of layers containing integrated circuit chips (ICs), thereby obtaining high-density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. A unique aspect of this invention is that it provides a low cost method of stacking commercially available IC's in BGA packages while allowing the independent routing of several non-common UO (input/output) signals from upper-level layers to lower layers or to the bottom of the stack. Cost reduction is accomplished by utilizing relatively low cost interposer boards as appropriate to reroute leads to an access plane and by the ability to stack pre-packaged and pre-tested off-the-shelf BGA packages.

None of the background art addresses the need for compact, dense microelectronic stacks that take advantage of the high speed and small outline of a BGA package that are low cost and highly reliable and incorporate known good die (KGD), each aspect of which the instant invention addresses.

SUMMARY

The present invention provides stackable layers which may be interconnected to form a high-density electronic module. This application further discloses a stack of layers electrically interconnected in the vertical direction, suitable for mounting onto a PCB (printed circuit board) or other electronic device. This application further discloses a method for starting with standard BGA packages and manufacturing a stacked IC-containing package using interposer interconnections which are routed in the vertical direction along one or more access planes.

The invention generally consists of BGA packaged die that are electrically interconnected to conductive traces which terminate on an access edge. The conductive traces that terminate at the access edges are electrically rerouted to the desired locations in the stack to allow the interconnection of several non-common signals (e.g., chip enable and/or data lines) from an upper layer to a lower layer of a stack of layers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a perspective view of ball grid array integrated circuit chip package illustrating, respectively, the top of the package and the ball grid array on the underside thereof;

FIG. 2 plan view of an interposer board with exemplar conductive traces, access leads and solder ball pads formed thereon;

FIG. 3 is a front sectional view of a ball grid array package and interposer board showing the conductive traces, solder balls and solder ball pads;

FIG. 4 is a side sectional view of a ball grid array package and interposer board after the elements have been soldered together and under-filled, creating a stackable layer;

FIG. 5 is a side sectional view of a stack of layers that have been under-filled and bonded and connected a bottom interposer board;

FIG. 6 shows a side view of stack of layers illustrating an access plane with access leads exposed after lapping;

FIG. 7 shows a side view of stack of layers illustrating an access plane with access lead interconnections between access leads on different layers.

FIGS. 8, 9, and 10 illustrate cross-sections of different ball grid array packaging formats.

FIG. 11 shows a stack of layers wherein the layers comprise prefabricated access leads formed as part of the internal printed circuit structure of the layer and FIG. 12 illustrates metallized traces and T-connect structures.

FIGS. 13, 14, 15, and 16 illustrate a preferred embodiment of different internal printed circuit structures of the layers of FIG. 11.

 DETAILED DESCRIPTION

Referring now to the figures where like numerals designate like elements among the several views, FIGS. 1A and 1B show the top and underside, respectively, of an integrated circuit die package, here a conventional ball grid array (BGA) packaged memory device 1 which includes solder balls 5 for electrical communication of signals and power into and out of the BGA package. Conventional BGA memory packages in fine grid array or micro grid array are readily available from a variety of commercial sources such as MICRON TECHNOLOGIES, INC. or SAMSUNG CORP.

FIG. 2 illustrates an interposer board 10 made of a dielectric material such as BT Resin from Mitsubishi and includes conductive traces 15. Conductive traces 15 include solder ball pads 20 for the receiving of solder balls 5. Conductive traces lead to and terminate at an access edge 25 on the interposer board to form access leads 30.

Conductive traces made of copper or other conductive material are formed on the interposer board in a manner similar to that used in printed circuit board manufacturing. The conductive traces are patterned on the interposer board using conventional photolithography techniques so as to form solder ball pads 20 for the receiving and electrical connection of solder balls 5. The interposer board may include a single layer of conductive traces 15 or, in an alternative embodiment, multiple layers of conductive traces (not shown).

To assemble the device, solder balls 5 of BGA package 1 are aligned and electrically connected to solder ball pads 20 as is shown in FIG. 3. An alternative embodiment includes the use of fine grid BGA packages or even bare die that include ball bonds or that are adapted to be received by the solder ball pads. The BGA package and interposer board are then reflow-soldered using conventional reflow solder techniques. While the solder balls will self-align with the solder ball pads during solder reflow, reflow process controls are critical during soldering, particularly when utilizing fine pitch ball grid array packages. Solder reflow process controls such as those set forth in “MICRON TECHNOLOGY INC. Technical Note TN-00-11 SNIT BGA Assembly Design Recommendations” provide guidance for BGA reflow solder processes.

Upon completion of the reflow process, a stackable BGA layer 35 is formed as is illustrated in FIG. 4. The layer is then preferably under-filled with a suitable under-fill material 36 such as EPOTEK U-300 to provide structural stability and to minimize temperature-related stresses due to CTE mismatch of the interposer board and BGA package. It is preferable to provide sufficient under-fill so as to extend slightly beyond the edge of the BGA package and interposer board as the under-fill eliminates voids along the access edge 25 which will be utilized as discussed further below.

Turning now to FIG. 5, multiple layers 35 may be bonded together using a suitable adhesive or epoxy 37 such as EPOTEK 353 to form a three-dimensional stack 40 of layers 35, forming at least one access plane 45.

Mechanical assembly of multiple layers consists generally of aligning two or more layers 35 in a suitable fixture and bonding together using the appropriate adhesive. After the adhesive has cured, the sides of stack 40 that include access leads 30, i.e., access plane 45, are ground and lapped to expose the access leads as is illustrated in FIG. 6.

FIG. 7 shows how access leads 30 may be rerouted between layers as desired by using conventional photolithography and plating techniques to create conductive interconnecting metallic buses or traces 50. Alternatively, the entire access plane 45 may be metallized or coated with conductive material and the desired access leads isolated or interconnected by selectively removing conductive material using laser ablation, saw-cutting, etching or similar process. It is important that access plane be very planar with no voids to ensure the integrity of the layer interconnects. The stack is preferably encapsulated with a suitable encapsulant to protect interconnecting traces 50.

In an alternative preferred embodiment, shown in FIGS. 8, 9, and 10, the use of a separately fabricated interposer board 10 may be avoided by providing a prefabricated stackable layer 35 comprising a known good die (KGD) wherein access leads 30 are integrated within and as part of the internal structure of stackable layer 35 and are accessible on a lateral surface of the layer.

FIGS. 8, 9, and 10 show a cross-section of typical BGA packaging formats illustrating an integrated circuit die 100, an encapsulant 110 and an internal printed circuit structure 120 used for the routing of electrical signals from die 100 to solder ball pads 20 accessible on the lower major surface of the layer. As in well-known in the art of ball grid array manufacturing, die 100 (preferably a burned-in and pretested, aka known good die) is electrically connected to an internal printed circuit structure by means of, for instance, wire bonds, solder, conductive epoxy or flip chip means such that the bond pads of the die are in electrical connection with solder ball pads 20 as part of the ball grid array manufacturing process. The entire assembly is encapsulated in a suitable encapsulant such that the solder ball pads are accessible for receiving a solder ball if desired.

In the illustrated embodiments of FIGS. 8, 9, and 10, at least one of the solder ball pads 20 is also electrically accessible on a lateral surface of the stackable layer 35 by means of an access lead 30. The embodiments of FIGS. 8, 9, and 10 of the stackable layer 35 of the invention may be provided with or without solder balls 5 on solder ball pads 20. As seen in FIGS. 8, 9, and 10, conductive access leads 30 are disposed on a lateral surface of stackable layer 35 for interconnection to another stackable layer 35 in a stack of layers 40 using, for instance, metallized T-connect structures.

Such a package format can optionally be manufactured with access leads 30 exposed on a lateral surface or, alternatively, in a form where a predetermined portion of the encapsulant of the package is removed by the user as described above to expose access leads 30.

When provided in this embodiment, the stackable layers 35 can optionally have solder balls applied to solder ball pads 20 and be used in conventional ball grid array applications. Alternatively the stackable layers may be provided without solder balls and be stacked with the base reroute substrate 130 of FIG. 11 and electrically interconnected by means of a metallized trace 50 to define a T-connect 140 of FIG. 12 on access plane 45 and access leads 30 to form a three-dimensional module 40.

In the preferred embodiment of FIG. 11, incorporating, for instance, DDR2 memory chips, a plurality of stackable layers 35 without solder balls are bonded to form a stacked electronic module 40. Each layer 35 comprises an encapsulated integrated circuit die 100 bonded to an internal printed circuit structure 120 comprised of a plurality of conductive traces, certain or all of which terminate on a lateral surface to define one or more access leads 30. One or more access leads 30 are electrically accessible on the lower surface of the layer on a corresponding solder ball pad 20. Solder ball pad 20 may selectively be provided with or without a solder ball but, in the illustrated embodiment, is provided without a solder ball to facilitate stacking.

Each internal printed circuit structure 120 in the stack comprises at least one impedance controlled, layer-specific access lead (CS and ODT in this instance) to allow selective layer circuitry control of a particular chip function by a user. The respective layer control access leads are horizontally off-set by a predetermined distance upon the selected lateral or longitudinal surface to allow the electrical isolation of a metallic trace or bus 50 upon the surface. Each layer-specific internal conductive structure is preferably designed whereby predetermined layer-specific impedance requirements are considered to optimize circuit performance.

Turning to FIGS. 13 through 16 of the illustrated embodiment, it is noted that selected layer-specific (e.g., Layers 1-4) access leads, in this case Clock Enable (CE), On Die Termination (ODT) and Chip Select (CS) access leads are each offset a predetermined horizontal distance (i.e., staggered) on the respective lateral surface. When assembled as a stack of layers as illustrated in FIG. 11, the aforementioned signal lines are accessible using the metallized traces 50 and T-connect structures 140 of FIG. 12 on a layer-by-layer basis while user-defined other access leads (e.g., Address or Data lines, VDD, VSS) on each of the layers are in vertical registration with each other to allow common electrical connection for each layer in the stack.

In this manner, when a plurality of stackable layers are bonded into an integral module wherein a substantially planar lateral surface is defined, a set of conductive traces may be defined thereon that provide a common electrical connection to all layers (e.g., address or data lines, VDD, VSS) and layer-specific control traces are electrically isolated so that preselected chip functions may be individually performed or controlled.

In this manner a high capacity, multi-layer module is provided that is low cost and which is readily received into existing BGA footprints.

From the foregoing description, it will be apparent the apparatus and method disclosed in this application will provide the significant functional benefits summarized in the introductory portion of the specification.

The following claims are intended not only to cover the specific embodiments disclosed, but also to cover the inventive concepts explained herein with the maximum breadth and comprehensiveness permitted by the prior art.

Many alterations and modifications may be made by those having ordinary skill in the art without departing from the spirit and scope of the invention. Therefore, it must be understood that the illustrated embodiment has been set forth only for the purposes of example and that it should not be taken as limiting the invention as defined by the following claims. For example, notwithstanding the fact the elements of a claim are set forth below in a certain combination, it must be expressly understood that the invention includes other combinations of fewer, more or different elements, which are disclosed above even though not claimed in such combinations.

The words used in this specification to describe the invention and its various embodiments are to be understood not only in the sense of their commonly defined meanings, but to include by special definition in this specification structure, material or acts beyond the scope of the commonly defined meanings. Thus, if an element can be understood in the context of this specification as including more than one meaning, then its use in a claim must be understood as being generic to all possible meanings supported by the specification and by the word itself.

The definitions of the words or elements of the following claims are, therefore, defined in this specification to include not only the combination of elements which are literally set forth, but all equivalent structure, material or acts for performing substantially the same function in substantially the same way to obtain substantially the same result. In this sense it is therefore contemplated that an equivalent substitution of two or more elements may be made for any one of the elements in the claims below or that a single element may be substituted for two or more elements in a claim. Although elements may be described above as acting in certain combinations and even initially claimed as such, it is to be expressly understood that one or more elements from a claimed combination can in some cases be excised from the combination and that the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Insubstantial changes from the claimed subject matter as viewed by a person with ordinary skill in the art, now known or later devised, are expressly contemplated as being equivalently within the scope of the claims. Therefore, obvious substitutions now or later known to one with ordinary skill in the art are defined to be within the scope of the defined elements.

The claims are thus to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, what can be obviously substituted and also what essentially incorporates the essential idea of the invention.

Claims

1. An integrated circuit package comprising:

an encapsulated integrated circuit die including a bond pad; and
an internal printed circuit structure configured to electrically connect the bond pad to a conductive pad disposed on an outer surface of the integrated circuit package, wherein the internal printed circuit structure includes: a first access lead electrically connected to the bond pad and to the conductive pad, wherein at least a portion of the first access lead is exposed on a lateral surface of the integrated circuit package; and a second access lead electrically isolated from the first access lead.

2. The integrated circuit package of claim 1, wherein the integrated circuit package is a ball grid array integrated circuit package.

3. The integrated circuit package of claim 1, wherein the integrated circuit die is a pretested integrated circuit die.

4. The integrated circuit package of claim 1, wherein the integrated circuit package comprises a first conductive T-connect structure electrically connected to the first access lead and configured to form an electrical connection with a second integrated circuit die.

5. The integrated circuit package of claim 4, wherein the integrated circuit package includes a second conductive T-connect structure electrically connected to the second access lead and configured to form an electrical connection with a third integrated circuit die.

6. The integrated circuit package of claim 1, further comprising a solder ball coupled to the conductive pad.

7. The integrated circuit package of claim 1, wherein the conductive pad is electrically connected to the bond pad by a wire bond.

8. The integrated circuit package of claim 1, wherein the conductive pad is electrically connected to the bond pad by a ball bond.

9. The integrated circuit package of claim 1, wherein the conductive pad is electrically connected to the bond pad by a conductive epoxy.

10. The integrated circuit package of claim 1, wherein the integrated circuit die comprises a DDR2 memory chip.

11. The integrated circuit package of claim 1, wherein the second access lead is electrically connected to a second bond pad of the encapsulated integrated circuit die and to a second conductive pad disposed on the outer surface of the integrated circuit package, and wherein at least a portion of the second access lead is exposed on the lateral surface of the integrated circuit package.

12. The integrated circuit package of claim 1, wherein the first access lead comprises a clock-enable access lead, an on-die termination access lead, or a chip-select access lead, and wherein the second access lead comprises another of a clock-enable access lead, an on-die termination access lead, or a chip-select access lead.

13. The integrated circuit package of claim 1, wherein at least one of the first or second access leads comprises an address or data access lead or a voltage supply access lead.

14. An electronic module comprising:

a first layer including: a first encapsulated integrated circuit; and an internal printed circuit structure configured to electrically connect the first encapsulated integrated circuit to a conductive pad disposed on an outer surface of the integrated circuit package, wherein the internal printed circuit structure comprises a first access lead electrically connected to the first encapsulated integrated circuit and the conductive pad, and wherein at least a portion of the first access lead is exposed on a lateral surface of the electronic module;
a second layer including: a second encapsulated integrated circuit; and a second access lead having a portion exposed on the lateral surface of the electronic module, wherein the second access lead is electrically connected to the second encapsulated integrated circuit; and
a conductive trace disposed on the lateral surface of the electronic module and configured to electrically connect the first access lead to the second access lead.

15. The electronic module of claim 14, wherein the internal printed circuit structure of the first layer includes a third access lead electrically isolated from the first access lead, and wherein the third access lead is electrically connected to the first encapsulated integrated circuit and is exposed on the lateral surface of the electronic module.

16. The electronic module of claim 15, wherein the third access lead is electrically connected to a second conductive trace that is disposed on the lateral surface of the electronic module and that is configured to electrically connect the first encapsulated integrated circuit to a third encapsulated integrated circuit of a third layer.

17. The electronic module of claim 14, further comprising a base reroute structure electrically connected to at least one of the first layer or the second layer via the conductive trace.

18. The electronic module of claim 14, wherein the conductive trace is electrically connected to the first access lead via first conductive T-connect structure and to the second access lead via a second conductive T-connect structure.

19. The electronic module of claim 14, wherein at least one of the first or second encapsulated integrated circuits comprises a memory chip.

20. The electronic module of claim 14, wherein at least one of the first or second encapsulated integrated circuits comprises a pretested integrated circuit die.

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Patent History
Patent number: 7982300
Type: Grant
Filed: Mar 25, 2010
Date of Patent: Jul 19, 2011
Patent Publication Number: 20100181662
Assignee: Aprolase Development Co., LLC (Wilmington, DE)
Inventors: Keith Gann (Tustin, CA), W. Eric Boyd (San Clemente, CA)
Primary Examiner: Jasmine J Clark
Application Number: 12/731,970